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MSP430FR5989-EP: Timer Clock Problem

ozgur yildiz
Prodigy 50 points
Part Number: MSP430FR5989-EP
Other Parts Discussed in Thread: MSP430FR5989

Tool/software:

Hello,

I am using msp430fr5989 MCU and we would like to create a timer signal by using Timer_B. I have external oscillator which is 32678 Hz and I would like to create a clock signal with same frequency. Unfortunately, I got approximately 8192 Hz and we did not find the reason of it. I am sharing the code snippet of configuration of it. 

CSCTL0_H = CSKEY_H;
CSCTL1 = DCOFSEL_0;
CSCTL2 = SELA_LFXTCLK | SELS_DCOCLK | SELM__DCOCLK;
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;
CSCTL4 &= ~LFXTOFF;
CSCTL0_H = 0;

TB0CCR0 = 1;
TB0CCTL0 = CCIE;
TB0CTL = TBSSEL__ACLK | MC__UP ;

Any help will be appreciated. 

Regards.

  • 0
    Guru 90990 points

    1) You won't succeed at generating 32kHz from a timer using ACLK (at 32kHz). The core problem is that the timer would have to generate 2x output edges (rising/falling) based on a single input clock edge (rising). 

    2) You might succeed (with a fast enough MCLK) at generating an output clock by toggling a GPIO based on a timer interrupt, but it will jitter when your code tries to do anything else. Better is to use one of the OUTMOD-s.

    3) You can output ACLK directly on P5.2 or PJ.2 [Ref data sheet (SLASEC9) Sections 5.11.24.9 and 5.11.24.20].

    [Edit: Minor clarification.]

  • 0 in reply to Bruce McKenney47378
    Prodigy 50 points

    Hello,

    Thanks for your reply. My question is that why is it quarter of ACLK frequency. Should it half of ACLK frequency?

    Regards.

  • +1 in reply to ozgur yildiz
    Guru 90990 points

    Referring to User Guide (SLAU367P) Fig 26-3: TB0R spends 1 (input) clock at =0, then 1 clock at =1, then cycles back to =0. That's a divide by 2. (It's typical to set CCR0=(Period-1).)

    You didn't show your ISR, but I expect it toggles the output pin, contributing half an output cycle each call. That's another divide by 2.

    With a very short timer period, the ISR may not have time to complete before the next interrupt, so the output will be limited by the speed of the ISR. I don't think this is your case now, since you have 2*31=62 MCLKs to work with, but with e.g. CCR0=0 (31 MCLKs) you would be very close.

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