MSP430FR5969: Configuring External 16Mhz Clock - OFIFG bit does not go low

Tool/software:

Hi all,

We are trying to use the MSP430FR5969 in a custom board that uses a 16Mhz ceramic oscillator(ABM8AAIG-16.00MHZ-V2R-T3). We are trying to configure the HFXT oscilltor as the clock source ,

we have referred the example code provided and have followed the same but the code is stuck in a loop at the end.

problem: The OFIFG Bit is never reset.This bit is a Oscillator Fault Flag that has to be cleared initially and then checked again but it is set after each clear.

testing: We are checking the SMCLK clk after the clock switch is done to verify that the switch has happened.Hence we have set the pin P3.4 as SMCLK.

if we remove the loop condition and test , the program runs. to check we implemented a pwm and ran it for 50%duty cycle of 8000 counts. if we calculate the actual freq available on a CRO we get around 5Mhz.

The code /Configuration we are doing:

void main()
{
    WDTCTL = WDTPW | WDTHOLD;   // stop watchdog timer
    PM5CTL0 &= ~LOCKLPM5; //Disable high Impendence

    P3DIR |= BIT4;                        // Output SMCLK
    P3SEL1 |= BIT4;                        //SMCLK Function select

     PJSEL0 |=  BIT6 | BIT7;      // For HFXT

     FRCTL0 = FRCTLPW | NACCESS_1;  //Wait state for the FRAM if clk is greater than 8Mhz

     CSCTL0_H = CSKEY >> 8;                    // Unlock CS registers
     CSCTL1 = DCOFSEL_6;                       // Set DCO to 8MHz
     CSCTL2 = SELA__LFXTCLK | SELS__HFXTCLK | SELM__HFXTCLK;
     CSCTL3 = 0;     // Set all dividers to 1

     CSCTL4 = HFXTDRIVE_3 | HFFREQ_3;  //Give max drive and freq range 16-24

Mhz

    do
    {
       CSCTL5 &= ~(HFXTOFFG);       // Clear XT1 and XT2 fault flag

       SFRIFG1 &= ~OFIFG;
     }while (SFRIFG1&OFIFG);                  // Test oscillator fault flag

    CSCTL0_H = 0;                               //LOCK CS

           while(1)
           {
               ;
           }

    }

any advice is much appreciated

Thank you