MSP430FR5969 hardware problem at 16MHz

The steps I mention are documented in the errata SLAZ473Q issues CS3 and CS12.

Yes, it's described there but the problem is that the workaround provided does not seem to work. If you check my code you can see that the clock init is copied from your errata. Could you verify on your side it still fails and ideally provide a workaround?

Also cranking up FRAM wait states to maximum has no effect. 

Olli,

I'm not understanding your clocking situation here. First you set the DCO to 1MHz then do MCLCK/2 and SMCLK/32. Then you do the 16MHz workaround and come out as MCLCK=16MHz/2 and SMCLK=16MHz/32. Then after your Init loop, you reset all dividers to 1, which makes MCLK =SMCLK=16MHz.

I would suggest cutting out the middle exercises and set your clocks appropriately from the beginning. This will allow you to avoid triggering the errata and potential resets.

Also for your PWM to work properly, you need to set the GIE bit to allow interrupts the PWM API uses. You can do this when you go to LPM0.

It will crash if I do that. That back an forth was reached by trial and error which allowed this simple test program to run. Hence the comment in OP that moving the clock change to the init() routine will fail.  I'm actually not (intentionally at least) changing SMLK to 16MHz, it stays at 8MHz as far as I know.

For the sake of argument, here's adjusted code which will die consistently before it gets to the 2nd port setup line. In fact it will run away from the debugger when it crashes i.e. it'll revert back to free run state by itself. 1st time the init routine is executed it'll get to the 1st port setup line and will crash, on 2nd round it will not get past the 1st initclocksignal line.

#include "driverlib.h"
// 1KHz 50/50
#define TIMER_PERIOD  31
#define DUTY_CYCLE  15

void init(void);

void main(void)
{
    //Stop WDT
    WDT_A_hold(WDT_A_BASE);


    /*
     * Disable the GPIO power-on default high-impedance mode to activate
     * previously configured port settings
     */


    init();
/*    __delay_cycles(0xE);
    CS_initClockSignal(CS_MCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_1);
*/
    //Enter LPM0
    __bis_SR_register(LPM0_bits);

    //For debugger
    __no_operation();

}

void init(void){
	FRAMCtl_configureWaitStateControl(1);
    CS_initClockSignal(CS_MCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_1);
    __delay_cycles(0xFF);
    //Set SMCLK = DCO with frequency divider of 32 = 500kHz
    CS_initClockSignal(CS_SMCLK,CS_DCOCLK_SELECT,CS_CLOCK_DIVIDER_32);
    __delay_cycles(0xFF);
	uint16_t tempCSCTL3 = 0;
	CSCTL0_H = CSKEY_H; // Unlock CS registers
	// Assuming SMCLK and MCLK are sourced from DCO
	// Store CSCTL3 settings to recover later
	tempCSCTL3 = CSCTL3;
	/* Keep overshoot transient within specification by setting clk sources
	to divide by 4*/
	// Clear the DIVS & DIVM masks (~0x77)and set both fields to 4 divider
	CSCTL3 = CSCTL3 & (~(0x77)) | DIVS__4 | DIVM__4;
	CSCTL1 = DCOFSEL_4 | DCORSEL; // Set DCO to 16MHz
	/* Delay by ~10us to let DCO settle. 60 cycles = 20 cycles buffer +
	(10us / (1/4MHz))*/
	__delay_cycles(0x60);
	CSCTL3 = tempCSCTL3; // Set all dividers
	CSCTL0_H = 0; // Lock CS registers

    //P1.4 as PWM output
    GPIO_setAsPeripheralModuleFunctionOutputPin(
        GPIO_PORT_P1,
        GPIO_PIN4,
        GPIO_PRIMARY_MODULE_FUNCTION
        );
    //P2.6 as PWM output
    GPIO_setAsPeripheralModuleFunctionOutputPin(
        GPIO_PORT_P2,
        GPIO_PIN6,
        GPIO_PRIMARY_MODULE_FUNCTION
        );
    PMM_unlockLPM5();

    //Generate PWM - Timer runs in Up mode
    Timer_B_outputPWMParam param = {0};
    param.clockSource = TIMER_B_CLOCKSOURCE_SMCLK;
    //PWM clock = 31.25kHz
    param.clockSourceDivider = TIMER_B_CLOCKSOURCE_DIVIDER_16;
    param.timerPeriod = TIMER_PERIOD;
    param.compareRegister = TIMER_B_CAPTURECOMPARE_REGISTER_1;
    param.compareOutputMode = TIMER_B_OUTPUTMODE_RESET_SET;
    param.dutyCycle = DUTY_CYCLE;
    Timer_B_outputPWM(TIMER_B0_BASE, &param);


}