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MSP430F247 - LFXT1 crystal - Low frequency Mode - Xcap settings - Internal capacitance - temperature drift

Kyle Butler
Prodigy 70 points

Other Parts Discussed in Thread: MSP430F247

Hi,

I'm working on a RTC temperature compensation process in a system based on MSP430F247.

I'm looking for informations about the temperature drift of the internal capacitances, Xcap setting, used as load capacitance for 32k crystal.

Does anybody have this kind of informations ?

Many thanks in advance.

  • 0
    Guru 227245 points

    Kyle Butler said:
    Does anybody have this kind of informations ?

    Not that I know. However, I don't expect much. Silicon capacitors are ideal capacitors. C=A/d. d changes with the physical expansion of silicon. It is 2.6*10-6=2.6ppm/K. However, A changes too over temperature, so it will compensate as it is squared.
    On a first glance, and assuming the capacitors built as plain silicon plate capacitors (vacuum/air dielectricum, or maybe SiO2), I'd assume a drift of +2.6ppm/K.

    This is based on some assumptions and a rather quick estimation, so don't take this as authoritative answer. :)

  • 0 in reply to Jens-Michael Gross
    Prodigy 70 points 
    Many thanks for your reply.

    So, if I well understood, when the temperature is rising of 1 degree celsius, a 10 pf capacitor is rising of 0.026 fF ?

    Which means that, over a variation of 50 degrees celcius, the same capacitor value will rise of 1.3 fF (50 times  0.026 fF). 
    Based on that, the drift of the integrated capacitors seems not to be the cause of my error.
  • 0 in reply to Kyle Butler
    Guru 227245 points

    Yes, that's what I think what's happening. Since the influence of teh capacitor on teh frequency is not that much, the temperature drift of the crystal itself would be the larger factor here.
    Remember that watch crystals are usually implemented as for oscillators. They have peak frequency on 25°C and a negative temperature coefficient in both directions. So for increasing temperatures, teh crystal drift is partly compensated by the capacitance drift while for sinking temperatures, the two add.

    However, no warranty for correctness. I actually do not know how TI really implemented the internal capacitors. It is only a guess. If a dielectricum other than vacuum/air or SiO is used, the values can be quite different.

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