MSP430 Timer Questions

Hi Jenitta,

If you have not come across this link, worth the look.

http://www.ti.com/lit/ml/slap113/slap113.pdf

Jenitta Rex said:

In the above case , both the interrupts are overflow interrupts or Capture/compare interrupts ? What is the difference between both Interrupt types ?

Each tiemr has one overflow interrupt. It is triggered when the timer counts to zero. This happens either when the timer overflows from 65535 to 0 (cont mode) or when the timer overflows from the value in CCR0 to 0 (in up mode). Manually setting the timer to 0 won't trigger the interrupt.

Compare interrupts are triggered when the timer counts to a value that is equal to the content of a compare register. When the tiemr counts up, it will eventually reach teh value of a compare register and this will trigger the interrupt. The timer will continue to count until it overflows. So a normal compare interrupt will happen once per timer cycle. But at different moments of the timer cycle. The frequency of the overflow interrupt and the compare interrupt are the same, but the phase is different. This is used for PWM generation.

Capture interrupts act on an external event. When e.g. a rising edge on an external port pin is detected, the current content of the timer count register is copied to the capture register and an interrupt is triggered. So independent of the moment the software executes the interrupt code, teh exact moment of the event (in relation to the timer count) is known.

Capture register and compare register are the same and switch roles depending on unit configuration. This is why the unit is called Capture/Compare unit and the register is known as capture/compare register (CCR). While a timer has only one overflow interrupt, it may have more than one CCR (up to 7) and therefore up to 7 different interrupts. The interrupt of CCR0 has its own interrupt vector whiel all others share the same wiht the overflow interrupt.

Now you don't want different interrupt frequencies with one timer. This is possible but not simple. The basic approach is to constantly reprogram the compare interrupt.
Assume the timer running with 1MHz clock, so each timer tick equals 1µs.

Setting CCR0 to 1000 would trigger an interupt 1ms after the timer overflow. However, the next interrupt woudl come 1ms after the next timer overflow, which is 65ms later. Not what you want. So the trick is to change the CCR value on each interrupt. Inside the ISR that was triggered 1ms after the timer overflow, we add another 1000 to the CCR register. So when the timer counts to 2000, another interrupt is generated. Exactly 1ms after the last, independent of code latency. Then anotehr 1000 is added to get an interrupt at a count of 3000 and so on. You can do this for each CCR independently to get different interrupt frequencies for them. The timer itself runs in cont mode from 0 to 65535. Because adding 1000 to 65000 (after 65 interrupts) rolls over to 464 (the timer register is a 16 bit unsigned int), the next interrupt will still come after 1000 timer ticks. No complex math needed.
This sound simple. So what's the problem?
The difficult part is that your program design must ensure that the ISR that does the increment is executed before the timer has passed the next trigger point. If you add 1000 to 1000, and the timer has already counted to 2001 due to other code being executed first (higher-priority interrupts, periods of disabled interrupts etc.) then no interrupt is triggered until the timer has done one complete cycle. Especially when dealing with multiple intervals in the same ISR, this may easily become an issue. And after all, you still want to do something when an interval is expired (or else you wouldn't need the different timings). Be sure it won't delay handling the next interrupt and compare register increment too much.