Hi.
Im currently using MSP430F519A. Normally, we use its interna clock for 16MHz, but now, for lowpower we want to use the external 32 kHz clock and change it whenever needed.
I have this code for using the internal a 16Mhz
//P7SEL |= 0x01; // Select XT1
P1DIR |= BIT0; // P1.0 output
P11DIR |= 0x07; // ACLK, MCLK, SMCLK set out to pins
P11SEL |= 0x07; // P11.0,1,2 for debugging purposes.
//UCSCTL6 |= XT1BYPASS; // Para OSC del RTC
// Initialize LFXT1
P7SEL |= 0x03; // Select XT1
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap
// Loop until XT1 fault flag is cleared
do
{
UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags
}while (UCSCTL7&XT1LFOFFG); // Test XT1 fault flag
UCSCTL4 = SELA_0 + SELS_3 + SELM_3; // Set ACLK = XT1 MCLK = DCOCLK
UCSCTL5 = DIVS_1;
UCSCTL3 = SELREF_0; // Set DCO FLL reference = XT1
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x00; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_7; // Select range for 16MHz operation
UCSCTL2 = 0x1E7; // Set DCO Multiplier for 16MHz
// 2* (N + 1) * FLLRef = Fdco
// 2 * (249 + 1) * 32768 = 16MHz
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 16 MHz / 32,768 Hz = 500000 = MCLK cycles for DCO to settle
__delay_cycles(500000);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
This works correctly.
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Now I want to select the external clock 32 kHz for use as Main Clock.
I tried different codes from the forum or the examples, but it never leaves the oscilltor fault loop :
P7DIR = 0;
P7SEL = 1; // External clock input on XIN
P7OUT = 0; // Initialize outputs to zero.
P11SEL = 3;
__bis_SR_register(SCG0|SCG1); // Disable FLL control loop
UCSCTL1 = DISMOD; // Disable modulation
// XT1 sourced externally, XT2 turned off, High Frequency Mode, Max drive capability for HF mode:
UCSCTL6 = XT1BYPASS | XT2OFF | XTS | XT1DRIVE0 | XT1DRIVE1;
UCSCTL6 &= ~XT1OFF; // Turn on XT1
UCSCTL3 = 0;
UCSCTL5 = 0;
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
SFRIFG1 &= ~OFIFG;
} while (SFRIFG1 & OFIFG); // <--- NEVER EXITS
What I'm doing wrong? How could I select the extenal clock for the main?
Thanks in advance.
