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msp430g2553 & usci30 errata

JeGeVa
Prodigy 20 points

Hello, is somebody having an exemple of code for working around usci30 errata (http://www.ti.com/litv/pdf/slaz440d)

that doesn't uses DMA ?

Thanks in advance

Sincerely

  • 0
    Guru 58965 points

    If the CPU clock is fast enough for the I2C clock you use and your code is efficient enough, that bug will not show up.

  • 0 in reply to old_cow_yellow
    Guru 58965 points

    Let me explain what I meant.

    Suppose there was no such bug (or TI fixed that bug), CPU or DMA must pickup RXBUF within about 8 I2C clocks. Otherwise there will be problems.

    Now, with this bug, CPU or DMA must pickup RXBUF within about 7 I2C clocks.

    Thus, you only need to be 8/7 = 115% as fast to avoid this bug.

  • 0 in reply to old_cow_yellow
    Prodigy 20 points

    Hello old_cow

    The thing is that here it is happening in LPM0 (CPUOFF) within an interrupt

    and (and per guide) the usci forces the DCO clock on (since smclk is sourced from there and the usci from smclk).

    The DCO in this exemple is running at 1MHz, the SMCLK @ 500khz (/2) and the usci @ 50khz (smclk/10)

    The thing is that in LPM0 i have no idea at what frq is running the component that takes care of the interrupts...

  • 0 in reply to JeGeVa
    Prodigy 40 points

    Hey, surprise surprise,

    just posted my problem here which is maybe the same as yours. Do you also have problems in master-receiver-mode? The second byte is aborted in my application which sounds like USCI30 from the errata. Maybe you could read my post, too? Is it an identical error?

    http://e2e.ti.com/support/microcontrollers/msp430/f/166/t/273974.aspx

    Dennis

  • 0 in reply to JeGeVa
    Guru 227245 points

    JeGeVa said:
    The thing is that in LPM0 i have no idea at what frq is running the component that takes care of the interrupts...

    An interrupt switches MCLK on which in turn activates its source (which is already still on in your case), so execution of the interrupt begins with the next MCLK cycle.
    Actualyl your'e even faster than in active mode because the interrupt can be handled immediately while in active mode, the CPU could be in the middle of a 6-cycle-instruction.

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