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MSP430FR5739 eUSCI I2C Bit 9 interrupt

Other Parts Discussed in Thread: MSP430FR5739

I keep getting a UCBIT9IFG interrupt flag. It is not enabled and I cannot find any reference to it in the Family Users guide. Could someone please tell me what it is and why it sets? 

Thanks

  • Never mind I found it. Used my thumbs instead of search.

  • Steve Varga said:
    It is not enabled and I cannot find any reference to it in the Family Users guide.

    Well, from the users guide (using the search in adobe reader):

    UCBIT9IFG
    This interrupt flag is generated each time the eUSCI_B is transferring 9th clock cycle of a byte of data. This gives the user the possibility to follow the I2C communication in software if wanted. The UCBIT9IFG is not set for address information.

    However, IFG bits are always set when the hardware event happens that they belong to. But they don't cause an interrupt unless the associated IE bit is set too.

  • Hi,

    Can you provide example code to put MSP430FR5739 controller on Low power mode 4.5 and wake up using interrupt from I2C ?

    Thanks and regards,

    Chethan

  • In LPM4.5, CPU, Ram, clock system and all peripherals are powered down except the port logic. So it is impossible to wake up from LPM4.5 by I2C.

    You may connect the SDA line with an interrupt-capable port pin (if not already on such a pin) and let the MSP restart when a negative edge is detected (start condition). However, this will restart the MSP (almost) as if it were just switched on. All peripherals have to be reconfigured as if power has just been switched on. So the USCI won't detect the already passed start condition and miss the transfer that has just awakened it.

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