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MSP430 timer input signal capture tick count oscillation issue

Anil Go
Prodigy 100 points

Hi,

I'm testing code using an MSP430F26x timer to capture the tick count of an input signal using timer B.  Timer B clock is a 10 kHz clock and Timer B tick count max is 10000 which rolls over every 1 second. The input signal is a 1 Hz external signal and its capture count is read every second by the code running on TBCCR2.

The following timer register setting is being used: MOV #CAP+CM_1+SCS+CCIE, &TBCCTL2

Sometimes an issue is seen where that the capture tick count register content oscillates between two adjacent ticks over several reads. So TBCCR2=10 is read at time N seconds and then TBCCR2=11 is read at time N+1 seconds followed by TBCCR2=10 being read at time N+2 seconds and so on for some seconds.

 I'd like to find out if this TBCCR2 oscillation could be happening because the 1Hz input signal occurs exactly at or slightly after 10 timer B ticks after timer B starts counting every second. I'd also like to find out if there's any way to mitigate this behavior of the MSP. Please let me know.

Thanks.

  • 0
    Guru 95585 points

    My first guess is the DCO clock modulator, which introduces jitter to fine-tune the (average) clock speed. The jitter pattern repeats every 32 "ticks", but if SMCLK/10kHz isn't a multiple of 32 the final timer tick will fall in a different place in the clock tick pattern each second. Of course, if you turn off the modulator you lose your calibrated SMCLK speed.

  • 0
    Guru 58965 points

    I think if you quadruple the Timer tick rate and quarter the captured count, you will get comparable results with less jitter.

    That is, clock the Timer at 40kHz from 0 up to 39999 and roll over every 1 second. When a count is captured in CCR2, shift it right 2-bits and take that as your result.

  • 0 in reply to old_cow_yellow
    Prodigy 100 points

    The timer clock currently is a fixed frequency in design, but I can suggest to the designers the clock 4x change you mentioned.

  • 0 in reply to Bruce McKenney
    Prodigy 100 points

    Does the DCO clock actually make an impact on a timer-based capture when the timer clock is configured as an input from an external clock?

  • 0 in reply to Anil Go
    Guru 58965 points

    No, under this circumstance the DCO clock has nothing to do with it.

    By the way, how stable is your 10 kHz used to clock the Timer? How stable is your 1 Hz being captured by the Timer? Can that be the cause of variation of captured counts? In that case, the variation is real and  what I suggested previously will not be able to reduce that variation.

     

  • 0 in reply to old_cow_yellow
    Prodigy 100 points

    Both the 1 Hz signal being captured and the 10 kHz clock signals used by the timer are stable signals. The 1 Hz signal being captured has less variance so it's more stable.

  • 0 in reply to Anil Go
    Expert 1620 points

    Anil

       Strictly out of curiosity, what results do you get if you don't set the SCS bit?

  • 0 in reply to Joseph Raslavsky
    Prodigy 100 points

    The behavior (timer capture tick oscillating) is similar between the two cases of the SCS bit being cleared/set, but occurs at different edges of the timer input clock.

    I mean that in one case the timer capture tick count varies when the captured signal is aligned with the rising edge of the INCLK, while in the other case the timer capture tick count varies when the captured signal with the falling edge of the INCLK. So depending on the phase offset between the captured signal and the timer clock (0 delay from INCLK rising edge or 1/2 clock delay from INCLK rising edge) the behavior shows up at different times.

    This seems to be similar to a quantizer output where the analog input offset could be set. So the digital output LSB could represent either (a) analog values between -1/2 and +1/2 of first quantizer step or (b) analog values between 0 and 1st quantizer step.

  • 0 in reply to Anil Go
    Guru 46710 points

    If 1Hz is derivative of 10KHz then it could be just race/uneven_skew condition and "problem" can be solved by sampling 1Hz at the other, opposite edge of 10KHz clock.

  • 0 in reply to Ilmars
    Guru 58965 points

    If either the 10 kHz clock or the 1 Hz signal has a 50 parts per million variation,  you would expect the captured counts to vary by 1 count within a couple of seconds.

    You said they are "stable". Do you mean down to 1 part per million? Or better than that?

  • 0 in reply to old_cow_yellow
    Prodigy 100 points

    Yes, stability was measured. Thanks.

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