• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 81 subscribers
  • Views 1798 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430F5232: 4-pin JTAG mode

Jason Kang
Intellectual 470 points
Other Parts Discussed in Thread: MSP430F5232, MSP430F5510

Hi. 

On MSP430F5232, I am planning to use “4-pin JTAG mode”. I want to confirm which signals need to be used to enable this mode. Beside four JTAG signals (TDO, TDI, TMS, TCK), two control signals seem to be the right ones: RSTDVDD/SBWTDIO & TEST/SBWTCK.

I believe I need to use TEST signal for sure. How about SBWTDIO signal? The description in the datasheet (SLAS897-Sept.2013) says “SBWTDIO is required to interface with MSP430 development tools and device programmers”. So, do I need to control SBWTDIO from the FPGA as well as TEST signal?

By the way, there a description on this issue in the forum’s thread called “MSP430F5510 4-wire JTAG entry sequence question”. It says “The 4-wire JTAG interface access is enabled by pulling the SBWTDIO line low and then applying a clock on SBWTCK (TEST).” Does it mean that “pulling SBWTDIO low” is a pre-condition of enabling 4-wire JTAG interface? If so, can I simply tie SBWTDOP to the GROUND while routing TEST (SBWTCK) to the FPGA?

Thank you. 

  • 0
    TI__Guru 63205 points

    Please take a look at Section 2.1 of the MSP430 Hardware Tools User's Guide (Rev. P) document to understand what is needed for 4-wire JTAG.

    This is found on the MSP430F5232 Product folder.

  • 0 in reply to BrandonAzbell
    Intellectual 470 points

    Hi, Brandon. 

    The document you introduced was very helpful. 

    By the way, I want to clarify something. 

    In Figure 2-1 on page 21/153 of the above document, the reset signal is called RST/NMI.

    For MSP430F5232, there is a signal called RSTDVDD/SBWTDIO (pin 45).

    I want to confirm with you if two signals are equivalent. 

    Thank you. 

  • 0 in reply to Jason Kang
    Guru 33653 points

    Jason Kang said:

    In Figure 2-1 on page 21/153 of the above document, the reset signal is called RST/NMI.

    For MSP430F5232, there is a signal called RSTDVDD/SBWTDIO (pin 45).

    I want to confirm with you if two signals are equivalent. 

    Thank you. 

    Typically, on MSP430F5xx devices, TEST pin is marked as TEST/SBWTCK, and RESET pin is marked as RST/NMI/SBWTDIO. On devices that have SBW (and all MSP430F5xx have it) for entry sequence are used both (TEST / RESET) pins. If you want to know more about TI SBW and 4-wire JTAG check...

     http://www.ti.com/lit/ug/slau320l/slau320l.pdf  slau320 MSP430 Programming Via the JTAG Interface

    Anyway, I prefer SBW because 4-wire JTAG occupies too many pins for my taste.

  • 0 in reply to zrno soli
    Intellectual 470 points

    Thank you for your feedback. 

  • 0 in reply to BrandonAzbell
    Intellectual 470 points

    Hi.

    While designing a circuit of "4-wire JTAG" for MSP430F5232, I was about to place a pull-up register (47 kohm) at the output of "RSTDVCC/SBWTDIO" as per the advice in Figure 2-1 in slau278p.

    Then, I realized the following.

    The note (6) on page 15 of (SLAS897-Sept 2013) indicates that "This non-configurable reset has an internal pullup to DVCC". It sounds like pull-up has been already done internally. 

    Does it mean that I can simply route this signal (pin 45, RSTDVCC/SBWTDIO) to the JTAG connector without placing the pull-up resistor & a capacitor (to the ground)?

    Thank you.  

     

  • 0 in reply to Jason Kang
    Guru 33653 points

    Jason Kang said:

    The note (6) on page 15 of (SLAS897-Sept 2013) indicates that "This non-configurable reset has an internal pullup to DVCC". It sounds like pull-up has been already done internally. 

    Does it mean that I can simply route this signal (pin 45, RSTDVCC/SBWTDIO) to the JTAG connector without placing the pull-up resistor & a capacitor (to the ground)?

    MSP430F5xx devices have internal pullup on RESET pin, and there is no need for external resistor (even you will find it on all TI MSP430F5xx dev boards).

    Capacitor on reset pin can be used to improve stability...

    http://www.embeddedrelated.com/groups/msp430/show/45367.php

  • 0 in reply to zrno soli
    TI__Guru 63205 points

    Another useful document to take a look at is the Designing with MSP430F522x and MSP430F521x Devices .

    I realize it is not found on the MSP430F5232 Product Folder, but it is appropriate as the MSP430F5232 has the dual-voltage rail implementation that is described in the above app note.

  • 0 in reply to zrno soli
    Intellectual 470 points

    Thank you for your confirmation. 

  • 0 in reply to zrno soli
    Guru 227245 points

    zrno soli said:
    MSP430F5xx devices have internal pullup on RESET pin, and there is no need for external resistor (even you will find it on all TI MSP430F5xx dev boards).

    Well, on 54xx (non-A) it is off by default, making it completely useless. Also, it is quite weak (~47k). On harsh environments, a stronger pullup is required.

    zrno soli said:
    Capacitor on reset pin can be used to improve stability...

    It also helps for proper startup if supply voltage is only slowly rising. When SBW is to be used, a 1k series resistor between RST and the capacitor allows for larger capacitance (on very slowly rising supplies) than 2.2nF.

**Attention** This is a public forum