MSP430F2618 SPI

From the MSP430F2xxx family users guide SPI is supported on both UCSI_A and UCSI_B so this indicates that it is possible to support a total of four seperate SPI ports with the basic hardware modules. You then need to check that the actual hardware in the chip you are using can support all of the required pins.

It is usually possible to drive multiple SPI peripherats from a single port provided that both master and sl;ave support an enable or chip select signal. I.E you simply connect SPI_CLK SPI_MOSI, and SPI_MISO to all the devices but uses a separate IO port for the chip select to each device. This will require that you manually control each chip select dependent on the device you want to communicate with.  

Hi Roy,

Thanks for your suggestions.

By the way you mean some thing like this:

different port pins for selecting my two separate devices like p2.1 to device1 and p2.2 for device2 where p2.1 is connected to device1 select pin and p2.2 to device2 select pin?

regards.

Yes, that is correct.

Use P2.1 to enable device 1

Do data transfers with device 1

Use P2.1 to disable device 1

Then follow same process for device 2 with P2.2

Hi Roy,

Thank you once again.

Regards.

And do not forget to pull-up your master's MISO input pin as there always be moments where neither of slaves are selected, theirs MISO outputs are tri-stated. Then you'll have spurious interrupts in your master SPI Rx...

Serge A said:

And do not forget to pull-up your master's MISO input pin as there always be moments where neither of slaves are selected, theirs MISO outputs are tri-stated. Then you'll have spurious interrupts in your master SPI Rx...

The master generates an interrupt after every 8th SPI clock cycle, no matter whether a slave is connected or not. And input changes on MISO won't do anything if the master isn't sending/clocking the bus.
Pull-ups are not required.

However, initial port pin states should be considered while the MSP is powering up and configuring the pins. All slaves should be selected and de-selected once before doing the first transfer, so they won't take transitions on the clock line during init as valid clock pulses. (or do something similar to ensure this, like having pull-ups on the CS lines etc.)

Jens-Michael, you are right, spurious interrupts is rather the case for UART, not SPI.
It is still good practice hardware-wise to pull up inputs that potentially can become floating (MISO can). This can prevent unexpected large current drawn from power supply. CMOS gates don’t like anything between logical 0 and 1 on inputs. Otherwise both transistors in the gate could get turned on, thus shorting the power supply and ground, which would cause large current and potentially destroy the CMOS gate. Even though modern MSPs have Schmitt triggers on most of theirs inputs preventing this dangerous behaviour, floating inputs acts as antennas injecting all sorts of interference into MSP circuitry.

Serge A said:

It is still good practice hardware-wise to pull up inputs that potentially can become floating (MISO can). This can prevent unexpected large current drawn from power supply.