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Help me increase the cpu clock on msp430 starting with this code?

Vern Yip
Intellectual 810 points
Other Parts Discussed in Thread: MSP430WARE

Hi, I have a MSP430 F5310. I want the CPU to run at the maximum speed possible.  I think that would be 25MHz system frequency.

I have a reference code below and I think it is set up to only run at 7.8MHz?

// Initialize DCO to 7.3728MHz
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation
UCSCTL2 = FLLD_1 | 224; // Set DCO Multiplier for 7.372800MHz (224+1)*32768 =7372800
__bic_SR_register(SCG0); // Enable the FLL control loop


I don't have an external oscillator so I have to use the internal DCO one I think.

Thanks

  • 0
    Guru 12050 points

    here is some more info, probably nee to increase core voltage too.

    http://e2e.ti.com/support/microcontrollers/msp430/f/166/t/215536.aspx

  • 0 in reply to Tony Philipsson
    Intellectual 810 points

    Based on what I've seen, it looks like if I want 19.6MHz, for example, I would set the DCORSEL and DCOx, and MODx values to;

    DCORSELx=7, DCOx=0, MODx=0; which has a range of 8.5 to 19.6MHz.

    So then the equation is

    F(dcoclk) = D x (N+1) x F(FllRefClock) / n

    D is FLL loop divider (FLLD bits)

    N is multipler bits in UCSCTL2 (FLLN bits)

    n is DCO tap selection in UCSCTL 0

    reference clock = 32768

    So that means, the equation is 2 x (300+1) x (32768) / 2 = 9.863168MHz.  

    ?? is that right?  The FLL divider will cancel out the divide by 2 from the ref clock.

  • 0 in reply to Vern Yip
    TI__Guru 56650 points

    Hi Vern,

    Tony was right, you need to make sure that the VCORE is set on the right level to run the CPU at higher speed:

    http://processors.wiki.ti.com/index.php/MSP430_FAQ#Running_CPU_at_higher_frequency_without_adequate_power_supply

    Since you are using MSP430F5xx device, I would also recommend to user the driverlib examples of MSP430ware. This will make things much easier for you to work with the UCS clock module.

  • 0 in reply to Vern Yip
    Guru 227245 points

    Vern Yip said:
    it looks like if I want 19.6MHz, for example, I would set the DCORSEL and DCOx, and MODx values to;
    DCORSELx=7, DCOx=0, MODx=0; which has a range of 8.5 to 19.6MHz.

    Vem, your conclusion does not exactly hit the point, even though it might work in this case. These settings do not ‘have a range from’ but produce exactly one single frequency somewhere in this range.
    Which one you get depends on the individual MSP.

    Using DCORSELx=7 means the DCO is (depending on DCOx and MODx) perhaps producing 32 different (1024 different average) frequencies in the range of 8.5 to 135 MHz, but guaranteed is only the range from 19.6 to 60MHz. Now the FLL can adjust the DCO up, so you will likely get your 19.6MHz (or something close, as there are only 1024 discrete averaged frequencies possible in this range, and only 32 stable/unmodulated/non-averaged ones). But worst case this means DCOx remains at 0, which will cause an oscillator fault signal and prevent you from using any of the crystals, as you cannot clear OFIFG then.
    And on many individual MSPs of this model, you will be unable to get a frequency significantly below 19.4MHz.

     Better use DCORSELx=6, which guarantees a range of 10.7 to 39MHz, so the 19.6MHz are somewhere in the middle, not causing a DCO fault being signaled.

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