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MSP430F149 UART-Idle-Line Multiprocessor

Evgeni
Prodigy 170 points

I can not get   URCTL:BRK  -flag and no interupt occur  after last reciving byte + 10bits(==1's) + any time more
all data bytes are reciving correctly (without any error)

I do:

main() { ... U0CTL=SPB|CHAR;  ...  ;  for(;;) {...  ;  U0RCTL = URXWIE|URXEIE; .... ;  LPM3 ...};}

interrupt[VECTOR_RX] void uart_rx (void)
{
  if (U0RCTL&RXERR    ) return;
  if (U0RCTL&RXWAKE ) {  if  (RXBUF0==cADR)  U0RCTL&=~URXWIE; return;  }
  buffer[++byte_cntr] = RXBUF0;
}

  • 0
    Prodigy 170 points

    I'm sorry, I precise my script:

    main() { ... U0CTL=SPB|CHAR;  U0RCTL = RXERR|BRK; ...  ;  for(;;) {...  ;    if (U0RCTL&BRK) { ....; U0RCTL=URXWIE|URXEIE; ME1|=URXE0; IE1|=URXIE0;....; }  ....LPM3 ...};}

  • 0 in reply to Evgeni
    Prodigy 170 points

    Unfortunately I realized my mistake: Break condition and Idle line condition are not the same.
    Break condition used (for example) for DMX-protocol
    I need identify end of reciving paket by idle line condition (MODBUS-protocol)
    Using of timer tick - it is a single way? No UART-hardware support?

  • 0 in reply to Evgeni
    Prodigy 170 points

    I need interupt after last data byte transmited (complite shift register output, no new data in tx-buffer).
    Can I use TXWAKE and put one more byte (dont care byte), when last valuable byte in shift register?
    I test this: but "dont care byte" has been appeared in output, why?

  • 0 in reply to Evgeni
    Prodigy 170 points

    Why there is no info in datasheet  about:

    if (P3SEL&BIT4)==0     UART0 TX is disabled (like ME1&=~UTXE0)

    Maybe I have mistake?

  • 0 in reply to Evgeni
    Prodigy 170 points

    Please give me sure about:

    if  ( ME1.UTXE0==0  &&  P3SEL.4==1) 
    than   P3.4  will work as input (regadless  P3DIR.4 or not)

  • 0 in reply to Evgeni
    Prodigy 170 points

    Don't worry about all of my questions above.
    I found answers (all problem is my mistake)

    I should notes about lack of information

    UART-TX is full empty, after writing 1 byte to TX-BUFFER:
        - UTXIFG0 going to 0
        - time (~ about one transmitting-bit)
        - UTXIFG0 going to 1

    There is no this information in datasheets, but it is necessary!!

  • 0 in reply to Evgeni
    Guru 227245 points

    You can use teh ARDY(IFG/IE) interrupt. It is flagged when the last transmission has been finished, based on the configuration. So it should happen if the last byte has been sent and TX buffer is empty.

    Of course your 'don't care' byte is being sent, as the hardware does not know that it is a don't care byte :)

     

     

     

  • 0 in reply to Jens-Michael Gross
    Prodigy 170 points

    Hardware know about "dont care byte"
    because TXWE-bit has been set,
    before "dont care byte" has been pushed into TXBUF

    In this case TX-output stay in "idle-line state"
    instead of trasmitting "dont care byte" wich has been pushed into TXBUF.

    This work properly
    I did mistake when set TXWE-bit into wrong address (special function register)

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