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Looking for msp432 Dhrystone 2.1 algorithm execution from SRAM

SLAS826A has a statement in section 5.9 that the Dhrystone 2.1 algorithm. Code execution from SRAM, stack and data in SRAM was used.

Are there any examples ( Dhrystone or otherwise ) showing execution of msp432 code in SRAM.

  • David,

    I am looking into this, but it seems the appropriate people to address this to are out on holiday until next week. Please stay tuned.

    Regards,
    JH
  • I would like to take advantage of the System Initialization support that is described in section 6.10 of SPNU151K ( ARM Optimizing C/C++ compiler User's Guide ).

    ( SLAA668 section 4.2 says: "Particularly on MSP432P401xx, SRAMs work at the

    same speed as the CPU clock frequency so code execution from SRAM clearly gives a performance and
    throughput advantage compared to code execution from flash. There is a power consumption advantage
    for SRAM compared to flash as well. Power consumption (commonly measured in μA/MHz) for SRAM is
    significantly lower than the μA/MHz consumption of flash memory. Therefore, TI recommends executing
    small loops or functions that are frequently used from SRAM instead of flash for performance and power
    benefits.
    This may be handled by using a smart function to copy a function or subset of code from flash to SRAM
    and execute from SRAM whenever needed."

    I guess I should cross-link to
        https://e2e.ti.com/support/microcontrollers/msp430/f/166/p/456985/1650130
    a
    nd
       https://e2e.ti.com/support/microcontrollers/msp430/f/166/p/456985/1710537 

    but both of these pages show techniques that seem to rather labor intensive.
    Are there easier ways that are more supported by the compiler?

  • Thanks Jace! I can wait - I'm just trying to capture the need for some clean examples that demonstrate the recommended techniques.
  • Hi David,

    David Dyck45 said:
     Are there any examples ( Dhrystone or otherwise ) showing execution of msp432 code in SRAM

    Please take a look at this post for the Dhrystone project. Runs from flash with no wait cycles.

     

    MSP432 DMIPS/MHZ - TI C compiler nowhere close to datasheet; GCC Linaro very close. - MSP low-power microcontroller...

    e2e.ti.com
    So I thought I'd try running the Dhrystone 2.1 benchmark on an MSP432 Launchpad; the datahseet for the MSP432R401 says it will do 1.196 DMIPS/MHz. I found with

    And for the SRAM example, please take a look at this project, this is another way to do it and might be simpler to follow/use.

    msp432_sample_ram_project.zip

      Best regards,

       David

  • Thank you,

    I'm revisiting this, and wanted to compare this sample with it's special lines in the msp432p401r.cmd link file SECTIONS 

    GROUP
    {
    .toggle: { toggle1.obj(.text)
    toggle2.obj(.text) }
    } load = FLASH, run = SRAM_CODE, table(_task1_copy_table)

    with the general hints from the wiki ( see below )
       ( note that the wiki page refers to the usage of copy_in used in the sample provided above as being targeted towards older compilers )

    I would like to use have finer control and use

    __attribute__((ramfunc))
     void f(void) { ... }

    on select functions in the source files.

    I tried to "add" this line (from the wiki ) to my linker cmd file

     .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT)

    Since I was working from the FFT example on the educational boosterpack the linker file I started with had different names

       .TI.ramfunc : {} load=MAIN, run=SRAM_CODE, table(BINIT)

    but this gets me the following error

     warning #10247-D: creating output section ".binit" without a SECTIONS specification

    I would really appreciate some hints to use the methods described in Placing_functions_in_RAM wiki page

    the wiki page didn't mention that we needed to add a .binit SECTION
    I made a guess and added

    .binit : > MAIN

    to my SECTIONS of the .cmd file

    I'm guessing that the .binit section should likely be similar and near the .cinit section

    I wasn't quite as confident in my guess of the placement of the .TI.ramfunc

      [[[ My question to experts, is the syntax and placement of .TI.ramfunc reasonable?

          what are cautions or improvements that could be made  ]]]

    Here is my SECTIONS

    SECTIONS
    {
    .intvecs: > 0x00000000
    .text : > MAIN
    .const : > MAIN
    .binit : > MAIN
    .cinit : > MAIN
    .pinit : > MAIN

    .flashMailbox : > 0x00200000

    .vtable : > 0x20000000
    .data : > SRAM_DATA
    .bss : > SRAM_DATA
    .sysmem : > SRAM_DATA
    .TI.ramfunc : {} load=MAIN, run=SRAM_CODE, table(BINIT)
    .stack : > SRAM_DATA (HIGH)
    }


    ---

    Reference information:

    Placing_functions_in_RAM wiki:   http://processors.wiki.ti.com/index.php/Placing_functions_in_RAM

    Advanced Linker Techniques for Convenient and Efficient Memory Usage:   http://www.ti.com.cn/cn/lit/an/spraa46a/spraa46a.pdf

    ARM Assembly Language Tools  v15.12.0.LTS:  http://www.ti.com.cn/cn/lit/ug/spnu118o/spnu118o.pdf  
      ( see section 8 Linker Description )

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