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MSP430FG6625 Master clock (MCLK) doesn't work with 24Mhz (XT2) clock.

Other Parts Discussed in Thread: MSP430FG6625, MSP430F5510, MSP430F5659

Hi,

I have a question regarding the 24Mhz clock which I am getting it from external XT2 cristal. I configure my code to use 24Mhz XT2 as the main clock for SMCLK and MCLK. I also verified on the scope that the SMCLK is getting 24 Mhz clock, but when I run my code it freezes  when I use __delay_cycle() to generate some microsecond delay.

I did some testing and I discover that my code executes with the same delay function when I configure the MCLK with (divide by 2)12 MHz frequency (f / 2).

My question is why my code never pass through the delay function?

It seems that the MCLK doesn't like the 24 MHz frequency. Is it true? Can I not run my MCLK at 24Mhz? If so then why not. I mean the spec says the MSP430FG6625 can support up to 32 MHz clock. 

FYI, following is the part of my code:

#define CYCLES_PER_US 24L 

#define DELAY_US(x) __delay_cycles((x * CYCLES_PER_US))

 

  WDTCTL = WDTPW + WDTHOLD; //Stop watchdog timer

 clock() //Configure clock  SMCLK=MCLK=XT2 (24Mhz)

  DELAY_US(550); //  <-----It stuck at this line of code when using 24Mhz for MCLK, but it pass thorugh when using 12Mhz for MCLK

printf("Executing the code\n");

 foo_func() //some function to call and execute rest of the code.

MY clock configure code:

void clock(){

CTSD16CCTL0 |= CTSD16SC; 


do{


CTSD16CTL &= ~CTSD16OFFG;
}while (CTSD16CTL&CTSD16OFFG); 

while(BAKCTL & LOCKBAK)
BAKCTL &= ~(LOCKBAK);

P7SEL |= BIT2; // Port select XT2
UCSCTL6 &= ~XT2OFF; // Enable XT2
UCSCTL3 |= SELREF_2; // FLLref = REFO
// Since LFXT1 is not used,
// sourcing FLL with LFXT1 can cause
// XT1OFFG flag to set
UCSCTL4 |= SELA_2; // ACLK=REFO,SMCLK=DCO,MCLK=DCO

// Loop until XT1,XT2 & DCO stabilizes - in this case loop until XT2 settles
do
{
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | /*XT1HFOFFG |*/ DCOFFG);
                                                                                // Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG;                                         // Clear fault flags
}while (SFRIFG1&OFIFG);                                 // Test oscillator fault flag

UCSCTL6 &= ~XT2DRIVE0;                            // Decrease XT2 Drive according to expected frequency


UCSCTL4 |= SELS_5 | SELM_5;                    // SMCLK=MCLK=XT2

}

Thanks.

  • The fSYSTEM specification in section 5.3 of the datasheet says that in the default condition, you must not go above 8 MHz.

    For how to increase VCORE, see section 2.2.4 of the User's Guide.

  • Clemens Ladisch said:

    The fSYSTEM specification in section 5.3 of the datasheet says that in the default condition, you must not go above 8 MHz.

    For how to increase VCORE, see section 2.2.4 of the User's Guide.

    Thank you for the information. This is the important part that was missing in my code, but even after implementing the correct Vcore level it didn't work. The Max level it has is level-3 which supports up to 20Mhz max and I am using 24Mhz. I guess I really don't have any other choice, but to stuck with 12 Mhz at Level-1 Vcore. 

  • XT2 supports up to 32 MHz, but that is only a clock source.

    MCLK (and the other clocks) are not allowed to go higher than 20 MHz, so if you have a 32 MHz crystal, you have to divide it down.

  • OK. I thought you could run at 24Mhz, but I was wrong. I am using 24Mhz crystal (XT2) and the only option I have is to divide it by 2 to get 12MHz max.
  • You could divide XT2 down and use it as reference for the FLL, to get a DCO clock of about 20 MHz. (This would be not very exact, and have jitter, but that does not matter much for SPI.)
  • Deepak Yadav said:

    It seems that the MCLK doesn't like the 24 MHz frequency. Is it true? Can I not run my MCLK at 24Mhz? If so then why not. I mean the spec says the MSP430FG6625 can support up to 32 MHz clock.

    BTW, I am running MSP430F5659 (max 20 MHz MCLK per datasheet) on 32 MHz MCLK directly form XT2 with max core voltage level. Also, MSP430F5510 on 48 MHz MCLK directly from XT2 with max core voltage level. (Didn't try, but) I deeply doubt that your device with max 20 MHz MCLK specified in datasheet can't be overclocked by 4 MHz more (with MCLK directly from XT2 with max core voltage level).