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This is something for the designers to think about for the future. Please pass it on.
I've been working with various flavors of the msp430 (msp430f1611, msp430f2618, msp430f5438a) and have recently switched over to the msp432p401r.
In the course of all this work I have some thought on how the registers are layed out for the eUSCIs on the msp432 and would like to share them. Having a different register layout (one that is more consistent) would greatly simplify what the s/w driver writers have to deal with when writing software for these modules.
Sameness is good, difference generates code and has to be dealt with.
Current layout:
Here is how I would have done it. Where possible I've kept the same offset for registers that behave the same..
Okay, I see you are arguing that there is benefit to maintaining consistency with other eUSCI modules.
But why? The code doesn't directly port. The msp432 references everything via structures. You can't reuse 430 code, its a completely different ISA). The I/O system is different, etc.
Because the module is referenced via pointers and structures, that takes care of any differences there might be in register layout between the msp432 and previous implementations.
I really don't see how replicating the old physical layout really buys you anything.
If you want to insist on the register layout MUST be compatible with other MCUs (which inherently are msp430s), I'd like you to explain why you think this is required. What does it actually buy you? How would it work? How does that allow one to reuse code and save time?
The default header file uses CMSIS-style structures, but MSP430-compatible definitions are still available in msp432p401r_classic.h, which allows to reuse old code for those modules.
Clemens Ladisch said:The default header file uses CMSIS-style structures, but MSP430-compatible definitions are still available in msp432p401r_classic.h, which allows to reuse old code for those modules.
yes and there is such a file describing what the basics of the chip look like for any of the chips. This hides what the actual details are from the code at the first level.
If the structure of the registers is cleaned up to allow better software (such as I suggested), these changes are still hidden wrt the naming which is what the previous code needs.
so any changes to the h/w still allow using the old code because it can be hidden by header files. So that's orthogonal to what I originally was talking about.
cleaning up the h/w architecture results in s/w that lays down better, is simpler, and easier to maintain because it doesn't have to deal with different ideosyncrocies that are currently there.
now this is somewhat moot, because TI isn't going to change the current h/w. But the point is maybe just maybe , they might clean it up in the future. What's weird is they had a structure in the msp430f5438a that was pretty clean and symetric. Not sure why the msp432 has it different again.
Changing the register offsets could break old code; it is perfectly valid to take the address of the first register and access the other ones with fixed offsets (see TI's driverlib). And any "cleanup" would require yet another module type (USCI → eUSCI → xUSCI?).
Making the A/B modules more consistent would be a good thing, but apparently, this doesn't outweigh the incompatibilities and confusion it would introduce.
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