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Tool/software: TI C/C++ Compiler
#include "msp430.h" #include "intrinsics.h" // defining flags as volatile(coz we use these variables in the main and in the ISR as well): volatile unsigned int timerCount = 0; //defines the millisecond counter volatile unsigned int normalPulse1=0; //defines another flag to indicates when 1 second has passed for normal pulse1 volatile unsigned int badPulse1=0; //defines another flag to indicates when 1 second has passed for bad pulse1 volatile unsigned int normalPulse2=0; //defines another flag to indicates when 1 second has passed for normal pulse2 volatile unsigned int badPulse2=0; //defines another flag to indicates when 1 second has passed for bad pulse2 volatile unsigned int secondsCount=0; //defines the seconds count for the bad pulse void main() { //Main function // configure watchdog timer: WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer P2OUT &= ~(BIT4); //preload 1pps to '0' // set I/O pins directions: P1DIR |=BIT6+BIT7; //set p1.x to 11000000 P2DIR |=BIT4; // Set P2.4 to output direction PJDIR |=BIT0+BIT1+BIT3; // set pj.x output 0000 1011 P2SEL |= BIT4; //select the option of using TD0.0 in pin 2.4 //P2IES |= BIT4; // high -> low is selected with IES.x = 1. //P2IFG &= ~(BIT4); // To prevent an immediate interrupt, clear the flag for // P2.4 before enabling the interrupt. //P2IE |= BIT4; // Enable interrupts for P2.4 // Configure XT1 (external oscillator): PJSEL |= BIT4+BIT5; // port select for xt1 UCSCTL6 &= ~(XT1OFF); //xt1 is on UCSCTL3 = 0; // FLL REFERENCE CLOCK REFERENCE = XT1 // configure TD0.0 (TimerD0.0): TD0CTL0 |=MC_1+ID_3+TDSSEL_0+TDIE+CNTL_0+TDCLR; //defining timer d TD0.0 (P2.4) upmode , devide by 8 , TDCLK , enable interupt , TD0CCR0=1600-1; // setting TAR count up value 1600 (12.8MHz / 8 = 1.6MHz , 1.6MHz / 1600 = 1000 Hz) when 1000 is passed means 1 second has passed as well //TD0CCR1 =400-1; // setting the duty cycle to 25% pulse TD0CCTL0 |= CCIE; //ENABLES CCIFG INTERUPT ON CCR0 //TD0CCTL1 |=CCIE; //ENABLES CCIFG INTERUPT ON CCR1 __enable_interrupt(); //enables interupts in the ISR for(;;){ // Main loop - Endless loop // EXTERNAL / INTERNAL SELECTION BY SW4 if ((P2IN & BIT2)==0){ // INTERNAL MODE PJOUT |=BIT3; // sends '1' from pj.3 output to the multiplexer U4 (uses the internal 1pps) //PULSE 1 : DESCRETE ON/OFF AND SWITCH ON/BAD/OFF if ((P2IN & BIT0)==0 || (P1IN & BIT0)==0) { //NORMAL SIGNAL OF 1PPS checks if descrete source is on or 1pps sw pulse 1 is on P1OUT |= BIT6; //ENABLES PULSE BY THE 'AND' GATE PJOUT |= BIT0; //ENABLES TTL TO RS232 CONVERTER (FOR DIFF OUTPUT) if(normalPulse1==1){ //checks if normalPulse1 is on from the ISR normalPulse1 =0; // sets normalPulse1 to 0 again so the ISR will generate the pulse P2OUT ^=BIT4; //generates 1pps out of p2.4 } } else { P1OUT |= ~(BIT6); //DISABLES PULSE BY SENDING A '0' TO THE AND GATE } if ((P1IN & BIT2)==0) { //PULSE 1 BAD SIGNAL checks if the 1pps sw bad pulse is on P1OUT |= BIT6; //ENABLES PULSE BY THE 'AND' GATE PJOUT |= BIT0; //ENABLES TTL TO RS232 CONVERTER (FOR DIFF OUTPUT) if(badPulse1==1){ //checks if badPulse1 is on from the ISR badPulse1=0; // sets badPulse1 to 0 again so the ISR will generate the pulse P2OUT ^=BIT4; //generates 1pps out of p2.4 } } //PULSE 2 : DESCRETE ON/OFF AND SWITCH ON/BAD/OFF if ((P2IN & BIT1)==0 || (P1IN & BIT0)==0){ //NORMAL SIGNAL OF 1PPS checks if descrete source is on or 1pps sw pulse 2 is on P1OUT |= BIT7; //ENABLES PULSE BY THE 'AND' GATE PJOUT |= BIT1; //ENABLES TTL TO RS232 CONVERTER (FOR DIFF OUTPUT) if(normalPulse2==1){ normalPulse2=0; // sets normalPulse2 to 0 again so the ISR will generate the pulse P2OUT ^=BIT4; //generates 1pps out of p2.4 } } else { P1OUT |= ~(BIT7); //DISABLES PULSE BY SENDING A '0' TO THE AND GATE } if ((P1IN & BIT3)==0){ //PULSE 2 BAD SIGNAL P1OUT |= BIT6; //ENABLES PULSE BY THE 'AND' GATE PJOUT |= BIT0; //ENABLES TTL TO RS232 CONVERTER (FOR DIFF OUTPUT) if(badPulse2==1){ badPulse2=0; // sets badPulse2 to 0 again so the ISR will generate the pulse P2OUT ^=BIT4; //generates 1pps out of p2.4 } } } else { //EXTERNAL MODE PJOUT |= ~(BIT3); //sends '0' from pj.3 output to the multiplexer U4 (uses the external 1pps) P1OUT |= BIT6; // ENABLES PULSE 1 P1OUT |= BIT7; //ENABLES PULSE 2 PJOUT |= BIT0; //ENABLES RS422 DIFF OUTPUT FOR PULSE 1 PJOUT |= BIT1; // ENABLES RS422 DIFF OUTPUT FOR PULSE 2 } } } //ISR FOR TIMERD0.0 - NORMAL/BAD PULSE 1 AND 2 #pragma vector = TIMER0_D0_VECTOR //GENERATES 1PPS EVERY 1s for normal pulse __interrupt void TIMER0_D0 (void){ //NORMAL PULSE 1 AND 2: if (++timerCount > 500) { // checks if the incrementation of timerCount reaches 500 (means 1 second has passed)toggling means doubling the time this is why we need to devide the time to a half. (1000/2=500) timerCount = 0; // resets the millisecond counter to 0 normalPulse1 = 1; //once it reaches 500 (1 second) normalPulse1 will be 1 normalPulse2 = 1; //once it reaches 500 (1 second) normalPulse2 will be 1 secondsCount++; } // BAD PULSE 1 AND 2: if (secondsCount == 2) { // checks if the incrementation of secondCount reaches 2 seconds for bad pulse (means 2 second has passed) secondsCount = 0; // resets the millisecond counter to 0 badPulse1=1; // once it reaches 2000( 2 seconds) the badPulse1 will be 1. badPulse2=1; // once it reaches 2000( 2 seconds) the badPulse2 will be 1. } }
I would be glad if you could look at the code and see if thats the right application for my project , ( the code has been compiled with no errors)
thanks
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