STE Problem, SPI-Mode

Peter said:

Unfortunately i don't understand

what the Table 20−1.UCxSTE Operation of the user guide SLAU056J whould like to tell me? Can anyone explain it to me?

Hi,

For UCMODE_1, the master enables the slave (to transmit & receive) with a logic high. In other words, the slave is enabled when UCxSTE = 1

On the other hand, for UCMODE_2, the master enables the slave with a logic low. UCMODE_1 & UCMODE_2 are the only 4-wire SPI modes.

If you're using the MSP in slave mode and 4-wire SPI, the STE pin will block the CLK input and disable the output driver on the SOMI pin.
Once STE goes low, the SOMI pin will switch to output mode and the clock pulses are accepted.

If you're using the MSP in master mode, the master can be disabled (this means, the SIMO pin is disabled and the clock output is disabled and the clock generation is stopped) if a second master pulls the STE line.Multi-Master SPI is relatively uncommon. And I think this mode has a serious design flaw as the STE state won't trigger any interrupt. And while it disables the clock and SIMO pins, it does not release any slave the amster might have selected. The other master cannot release it too and unless one intercepts the STE pin by routing it to an interrupt-capable port pin and do so fast enough, there will be two slaves active on the bus, making the multi-master setup unreliable.
The older USART module did not support 4-wire SPI in master mode - for a reason.

So the master may set only one STE pin low at a time, and shall do so sufficiently before starting to clock teh bus (sending the dummy byte). The slave, however, should detect the STE transitions (route the signal to an interrupt-capable port pin), so it can reset the SPI hardware once STE goes high again (as this might happen in the middle of a byte and won't clear the byte or the TX buffer, so you'll need to reset the SPI hardware then and maybe the protocol software state too) and prepare for the next transfer.

It's a good thing to set up the SPI slave while STE is high, feed it with a dummy status byte (which is the first byte the master will receive), so you'll get a TX interrupt as soon as the master begins clocking. This allows shortest reaction time. (at least I think the dummy byte isn't moved to the shift register as long as STE is high, due to the missing clock)

The UCMODE in the mentioned table means that there are two 4-wire SPI slave modes, one where SPI is active-low (this is the SPI default on most SPI devices) and active-high (actually inverted). It is not used on any SPI device I know of, but can be used to save an additional port pin if there are only two slaves, one can work on STE LOW and one on STE HIGH, so the masters port pin effectively switches between the two slaves. (Same for the master mode, with the restrictions mentioned above)

Hello,

 

We have similar question about STE pin.

 

In our case we are using MSP430F53xx with external Audio device(SPI).

MSP430 will be the master.

The slave audio device has "status pin" which will indicate if the device is busy or not.

 

So during slave busy, in order to stop the Master(MSP430) from transmitting 

is it a better idea to connect the "status pin" from slave to "STE pin" of MSP430?

 

Please let me know your suggestion.

 

Regards.

Ayus said:

So during slave busy, in order to stop the Master(MSP430) from transmitting
is it a better idea to connect the "status pin" from slave to "STE pin" of MSP430?

No. the STE just shuts up the output hardware (master and slave mode) and switches the master to slave mode (master mode only - obviously).

However, the software won't get an interrupt if this happens etc.

Also, thsi shouldn't happen in the middle of a transfer. All slaves I know of which have such a 'busy' pin go into busy mode only after receiving a command that causes them to do some action. And the master should know that it has sent such a command :)
So if the masters software has started an operation that makes de tevice busy, it should know htis anyway and ot try to do further transfers, until a check of the busy line (on a GPIO port) has revealed that the slave is no longer busy.

Anyway, most devices with a status pin also respond to SPi transfers witha 'I'm busy' reply of some kind. So the master can as well just poll until it gets a 'not busy' reply through SPI and then send the next command. (e.g. SD cards work that way)

 

Dear all,

We are trying to implement SPI in MSP430F5438A. (Implementing SPI in Atmega128 was simple) . here we receive Slave data before we command from master device. and we want to implement 4-wire SPI. STE (En) signal in msp430f5438A goes high even if we make it low.

could any one help  us in this matter. Below is the Code.

Thanks

CK

#include "msp430x54xA.h"

    long int j;
    int read;

    void SPI_Transmit(char);
    void delay();
    
    void main()
    {

        WDTCTL = WDTPW+WDTHOLD;                   // Stop watchdog timer
    
        P2DIR=0x1E;                    //SLP_TR ,RESET,IRQ,CLKM
         P3DIR=0xDB;
        P3SEL=0x3F;               // P3.4,5 = USCI_A0 TXD/RXD & P3.0,1,2,3 = SPI_STE/SPI_MOSI/SPI_MISO/SPI_SCLK
        P3OUT=0x01;                    //SS HIGH
        P2OUT=0x08;                    // SLP_TR SHOULD BE LOW,RESET HIGH
             
        UCB0CTL1 = 0x01;
        UCB0CTL1 = 0x81;       // CLK = ACLK
        UCB0CTL0 = 0x2D;
        UCB0BR0 = 0x00;
        UCB0BR1 = 0x00;
        //UCB0STAT=0xC0;   
        UCB0CTL1 = 0x80;       // **Initialize USCI state machine**
        UCB0IE=0x03;
    
        //while(1)
        //{
        P3OUT=0X00;                 // ss\ i.e., SELECTION low
        delay();
        SPI_Transmit(0x9C);            
        delay();
        SPI_Transmit(0x00);         
        delay();
        P3OUT=0X01;
        //}
                      
                  }
        
    void SPI_Transmit(char D)
    {
        while (!(UCB0IFG & UCTXIFG));             // USCI_B0 TX buffer ready?
          UCB0TXBUF = D;
          //while((UCB0STAT & 0x01));
          while(!(UCB0IFG & UCRXIFG));
          D = UCB0RXBUF  ;
        
    }   
        void delay()
    {
        for(j=0;j<30;j++)
        {
        }
    }   

First, it is a good idea to not assign anonymous hexadecimal values to configuration registers. Whicle I can look up in teh users guide what these bit smean, it is not sure whether they are actuall what you intended.

UCB0CTL0 = 0x2d; Should be rather witten as UCB0CTL0 = UCMM|UCMST|UCMODE_2|UCSYNC;

Now this tells us that you're running the MSP as master. Are you really in multi-master environment? Is there another master on the very same SPI bus?
If not, then both, setting UCMM and 4-wire-mode are nonsense.
STE is used to control the USCI, not to let the USCI control the slave. STE is an input, no output. If P3.0 is assigned to module usage (P3SEL=1), then setting bit 0 in P3OUT has no effect, nor has setting bit 0 in P3DIR. The USCI switches the P3.0 into input mode and uses it to control its own operating state.

So I guess, what you want is NOT multi master mode and NOT 4-wire mode. Use 3 wire mdoe isntead and use P3.0 as normal plain GPIO pin to control the slave.

Note that it makes no sense to let the USCI control the slave selection. Since SPI is a bus, there can be many slaves, each one with its own chip select signal. The SPI hardwar edoesn't knwo which one to select and for how many transfers. So it leaves the slave selection to the software.

Jens,

I'm a newbie, and I hesitated to reply to this since I have read many of your comments thus far and I know you know much more than I do about these things, but I really need to check this out since I am trying to get a CC1101 to talk to an MSP430G2553 via SPI.

My problem is that my UCB0CTL0 is coming out to be 0x2D like the other user in this post. Now I did use the mnemonics in my code - which produced the line:

UCB0CTL0 =  UCMSB + UCMST + UCMODE_2 + UCSYNC; 

- which is "trying" to set

1) the MSP430 as the master (with UCMST)

2) the SPI mode as "4-wire" (with UCMODE_2) - since I want to have other devices besides the CC1101 on the SPI

3) Synchronous mode (with UCSYNC)

4) MSB first (with UCMSB) - since the CC1101 manual specifies that MSB should be first. Section 14.3 of the CC1101 manual "Byte Synchronization" says "The MSB in the sync word is sent first.".

And now I am worried because I ended up with 0x2D any way I looked at it:

UCB0CTL0 =  (0x20) + (0x08) + (0x04) + (0x01) = 0x2D = 0b00101101

I did add UCCKPH to things at one point - because I saw an example with that - but I am not sure that would be right - and even if it is, I still get:

UCB0CTL0 = (0x80) + (0x20) + (0x08) + (0x04) + (0x01) = 0xAD = 0b10101101 - which is the same as before for the rightmost 7 bits - just with bit 7 = 1.

Please help me understand if I am doing something wrong - and how I can set the register properly without ending up with a 0x2D which means "multi-master". I am not trying to have "multi-master".

I have not run this yet since there are other things I need to configure (CC1101, sending/receiving packets, etc.) - but I want to try to get things as correct as possible before testing.

Sorry, again, if I am not understanding how to do this. All the mnemonics are still a bit confusing to me as I am trying to get registers set properly. So many of them mean the same thing "bit wise" (like UCMODE1 is the same as UCMODE_2 - so I used that one by mistake initially - and the CC1101 libraries define dozens of mnemonics which can be hard for us newbies to follow in the code).

 

 

JD said:

Please help me understand if I am doing something wrong - and how I can set the register properly without ending up with a 0x2D which means "multi-master". I am not trying to have "multi-master".

You too misunderstood the function and meaning of the STE pin (the 4th wire in 4-wire mode).
STE is an input. It does not control the external device, it allows external devices to control the MSP. If the MSP is master, this means there must be a second master on the bus, hence multi-master mode.
So if the MSP is the only master on the bus, use UCMODE_0.
To select the different slaves, you'll have to use plain GPIO signals, controlled by software. The USCI doesn't know which slave you want to select and when to start and end selection (as this depends on high-level protocol). Your software has to manually pull a GPIO pin that is connected to the slave's chip select pin, to make the slave listen and answer.
You may use the physical pin that is used for STE for this, but in GPIO mode then, and not selected as STE function.
And for two slaves, you need a second GPIO pin too.

Jens-Michael,

 

Thank you for your response and for clarifying this issue. Yes, now it makes sense - I am in a 3-wire SPI environment - with a GPIO CS control. In fact, based on the examples in hal_spi_config.c from the swra141 code I had the pins setup exactly as you describe - with the 3 SPI pins as peripheral module functions (I also have a UART for P1.1 and P1.2) - and the CS pin as a GPIO Output pin:

 

P1SEL = BIT1 + BIT2 + BIT5 + BIT6 + BIT7;  // P1.1=RXD, P1.2=TXD, P1.5=SCLK, P1.6=SOMI, P1.7=SIMO

P1SEL2 = BIT1 + BIT2 + BIT5 + BIT6 + BIT7;  // P1.1=RXD, P1.2=TXD, P1.5=SCLK, P1.6=SOMI, P1.7=SIMO

P2OUT |= BIT0;  // P2.0=CS for CC1101, Initial State High (Inactive)

 

Now I can use the same setup as the example for USCIB0 interface:

 

UCB0CTL0  = UCCKPH + UCMSB + UCMST + UCSYNC;

 

(which is 0xA9 (0b10101001) - rather than the 0xAD/0x2D.

 

My last question if you have time, do you have an opinion on using the UCCKPH with the CC1101? I have seen it used in some examples and not used in others. The hal_spi_config.c example uses it.

 

I read that the UCCKPH controls the clock phase - as far as whether the first or following edge is change or capture. But I do not know whether this is appropriate for the CC1101 - vs. the other SPI devices I plan to use ( 1. FRAM memory and 2. External calendar ). I come from the software side so I am not well versed in the "edge" subject matter.

Thanks again for helping me to understand the 3-wire vs. 4-wire SPI issue.

JD said:

But I do not know whether this is appropriate for the CC1101 - vs. the other SPI devices I plan to use ( 1. FRAM memory and 2. External calendar )

Good question. I don't know (I had to dig into the datasheets).
Basically, there are only four possible combinations of phase and polarity. If the target device contains a timing diagram, required phase and polarity can be

Basically, phase means that in one case, the data bit is put on the bus immediately (slave: when CS goes low, master: when you write to TXBUF) and on the first clock edge the data is captured, while on/after the second, the next byte is put on the bus (if any). The other case is that the bit is put on the bus at/after the first clock edge and captured on the second (when the clock is released). Both cases have pros and cons regarding timing (data hold times after the clock edge or data preload time before the edge etc.)

JD said:

I come from the software side so I am not well versed in the "edge" subject matter.

Problem is that data won't tell you when the next bit is sent (as both bits could be same value and you wouldn't detect a 'change' then. So you need a clock that tells you 'new data bit is available now ' and 'you may proceed to the next data bit now'
But processing the clock electrically is not an instant action. There's the electrical clock signal raising time, and the time it takes to tell the input shift register to capture data, and to perform the shift etc. So you need two events, signaling the beginning and the end of the period in which new valid data is on the bus: the two clock edges.

Jens-Michael,

Once again, thanks for the expertise - that was helpful regarding the clock phases.

Since - as a newbie - I like the forum items best when they are updated with results - here is an update:

1. I have successfully transmitted and received data with a pair of MSP430G2553 controlled CC1101's at this point - using a breadboard environment rather than any of the launchpad or development/experimental board setups.

2. So it appears using UCCKPH (Data is captured on the first UCLK edge and changed on the following edge) in my UCBxCTL0 setup did work for SPI with the CC1101 in my case.

Also, if it can help anyone in the future regarding a 3-wire SPI vs. 4-wire SPI question, I offer this:

One source of the confusion "might" be the terminology used in the MSP430 documentation vs. the CC1101 documentation.

A. In the CC1101 document swrs061h, Chapter 10 has the title "4-wire Serial Configuration and Data Interface" with the introduction "CC1101 is configured via a simple 4-wire SPI compatible interface (SI, SO, SCLK and CSn)".

B. From the MSP430 perspective, however, only 3 pins are configured to "enable peripheral module functions" - those being SCLK, SOMI and SIMO. The 4th wire is the CSn - which is just a GPIO output pin from the MSP430's perspective. So the MSP430 sees this setup as "3-wire SPI" - SCLK, SOMI and SIMO.

C. Additionally, there may be more wires when using the CC1101. For example, there may be a wire FROM the CC1101 GDO0 pin to a GPIO input on the MSP430 to handle interrupts, etc. Same for the GDO2 on the CC1101.

So the bottom line is that the CC1101 calls this "4-wire SPI" - but it is REALLY "3-wire SPI" on the MSP430 - AND it might really involve 4, 5 or 6 physical wires to do what you want with the MSP430 and the CC1101.

That's how I understand it at this point, anyway. Hopefully (he said with a small laugh) this will help somebody in the future.

Thanks for the help!

JD said:

Since - as a newbie - I like the forum items best when they are updated with results - here is an update:

Great! I too appreciate if the solutions/results are posted. Too often, people leave with a 'thanks, got it working', or no more feedback at all.

Thanks for posting.

Hi JD,

I want to config cc1101 using msp ( without any development board)
ie msp430g2553 will be connected to cc1101 they will communicate through spi. And then i want to configure the cc1101 in slave n msp 430 in master mode.
please Help me in this if you can or guide me. 

-Regards
Suresh Rai

Suresh,

What you are describing seems like it can certainly be done - and sound like they are, for the most part, what the msp430/cc1101/SPI elements are built to do.

You will need to safely power both the msp430 and the cc1101 - and then configure four of the msp430 GPIO pins for the SCLK, MOSI, SIMO and CSn. The cc1101 already has these (SCLK, SO, SI, CSn) defined on its side - so you will want to refer to the cc1101 datasheet for the pin definitions there.

Beyond that I am not sure where specifically you are needing help. I may or may not know a specific answer for you based on what you are asking.

I would suggest utilizing the TI tutorials and materials - especially the RF oriented help TI provides on the site.