Compiler/MSP430FR5969: SPI data fail

/*
 * DEF_FRAM.c
 *
 *  Created on: 23 de fev de 2017
 *      Author: chnmartins
 */
#include "DEF_FRAM.h"
#ifndef MODULE_DEF_FRAM_DEF_FRAM_C_
#define MODULE_DEF_FRAM_DEF_FRAM_C_

void FRCTL_Init(void)
{
	FRAMCtl_configureWaitStateControl(FRAMCTL_ACCESS_TIME_CYCLES_1);
}





#endif /* MODULE_DEF_FRAM_DEF_FRAM_C_ */

/*
 * CLK_SOURCES.c
 *
 *  Created on: 23 de fev de 2017
 *      Author: chnmartins
 */
#include "CLK_SOURCES.h"
void Clock_Init(void)
{
    /*
     * Sets the external clock source for XT1 and XT2. These variables can be used by
     * other API functions.
     *   XT1 Frequency -  32768 Hz
     *   XT2 Frequency -  14745600 Hz
     */
    CS_setExternalClockSource ( 32768, 14745600);
    CS_turnOnLFXTWithTimeout(LFXTDRIVE_3, 100000);  //Start Low Frequency crystal in low frequency mode
    //Start high frequency crystal
    //#define CS_HFXT_DRIVE_8MHZ_16MHZ (HFXTDRIVE_1)
    CS_turnOnHFXTWithTimeout(HFXTDRIVE_1, 100000);
    //Setting MCLK source from CS_HFXTCLK_SELECT with the divider of CS_CLOCK_DIVIDER_1.
    CS_initClockSignal (CS_MCLK, CS_HFXTCLK_SELECT, CS_CLOCK_DIVIDER_1);
    //etting SMCLK source from CS_HFXTCLK_SELECT with the divider of CS_CLOCK_DIVIDER_4.

    CS_initClockSignal ( CS_SMCLK, CS_HFXTCLK_SELECT, CS_CLOCK_DIVIDER_4);

    /*
     * Setting ACLK source from CS_LFXTCLK_SELECT with the divider of CS_CLOCK_DIVIDER_32.
     */
    CS_initClockSignal  (CS_ACLK, CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_32);

    /*
     * Set DCO frequency to 16000000 Hz
     */
    CS_setDCOFreq (CS_DCORSEL_0, CS_DCOFSEL_6);

    /*
     * Clears all oscillator fault flags including global oscillator fault flag
     * before switching clock sources
     */
    CS_clearAllOscFlagsWithTimeout(100000);

    /*
     * MCLK clock request enable. Setting this enables conditional module requests for MCLK
     */
    CS_disableClockRequest ( CS_MCLK);

    /*
     * SMCLK clock request enable. Setting this enables conditional module requests for SMCLK
     */
    CS_disableClockRequest (CS_SMCLK);

    /*
     * ACLK clock request enable. Setting this enables conditional module requests for ACLK
     */
    CS_disableClockRequest (CS_ACLK);
}

void Enable_SMCLK_Output_3P4(void)
{
    /* Port 3 Port Select Register 1 */
    P3SEL1 = BIT4;
    /* Port 3 Direction Register */
    P3DIR = BIT4;
}


void Init_HF_XTAL_PIN(void)
{
     //  XT1 Frequency -  32768 Hz
     //  XT2 Frequency -  14745600 Hz
     // Port 4 Interrupt Flag Register
     	P4IFG = 0;
     // Port J Output Register
     	PJOUT = 0;
     // Init Low frequency xtal pin
     	PJSEL0 = BIT4 | BIT5;
     // Init High Frequency Xtal Pin
        PJSEL0 = BIT6 | BIT7;
     // Port J Direction Register */
        PJDIR = 0;
}

void Start_up_clock_system(void)
{
	FRCTL_Init();
	Init_HF_XTAL_PIN();
	Enable_SMCLK_Output_3P4();
    Clock_Init();
}