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MSP430F233: WDT+ DCO SMCLK

Bjoern Femerling
Prodigy 100 points
Part Number: MSP430F233

Hello!

I got a question regarding the WDT+. I am using the Watchdog in Watchdog mode and I was trying to figure out how much time I have before it regenerates a PUC. The Counter Register is 16 Bit so it needs 65536 Clock ticks to Overflow.

As I read after a PUC the Watchdog is sourced from the DCO with 1.1MHz . If I don't change any of the settings it is supposed to be sourced by the SMCLK which gets sourced by the DCO if it isn't changed so I guess it keeps using the DCO if I change nothing in WDT or SMCLK Settings?

If the Controller starts normally is it just the same like after a PUC or is there a difference?

I've been reading the Users Guide but didn't find satisfying answers.

  • 0
    TI__Genius 15370 points

    Hi Bjoern,

    Bjoern Femerling said:
    As I read after a PUC the Watchdog is sourced from the DCO with 1.1MHz . If I don't change any of the settings it is supposed to be sourced by the SMCLK which gets sourced by the DCO if it isn't changed so I guess it keeps using the DCO if I change nothing in WDT or SMCLK Settings?

    Correct, for the MSP430FR233 the WDT's default source is SMCLK and the default SMCLK source is the DCO. So if you change none of the SMCLK or WDT source settings the WDT will be source from a 1.1MHz DCO as you've described.

    Bjoern Femerling said:
    If the Controller starts normally is it just the same like after a PUC or is there a difference?

    When you say the microcontroller starts normally, I'm assuming you mean that it is started by applying VCC. In this case the device undergoes a POR then a PUC and then enters Active Mode. You can see a diagram of device startup states in Figure 2-9 of the User's Guide.

    Finally, I recommend you take a look at some of the WDT examples in MSP430Ware. More specifically the msp430x24x_wdt_01.c example that can be found here. These show how to setup the WDT for an interval and the calculations that went into it. Let me know if you have any more questions.

    Best regards, 

    Caleb Overbay

  • 0 in reply to Caleb Overbay
    Prodigy 100 points
    Thanks! Still got one question though which didn't really get answered in there. It is about that divider /32768 that is confusing me. In the timer modules those dividers lower the frequenzies. so 1.1MHz divided by 32768 would be 33.57 Hz. The User Guide calls this an intervall even though this would be a Frequency. Is the Period of the 33.57Hz Frequency the supposed intervall? That would be 29.79 ms time expiring till the Counter would need to be reset.
    If the 33.57Hz are used to count up the Register it would take 65536/33.57 = 1952.22 Seconds. This seems way to long.
  • 0 in reply to Bjoern Femerling
    TI__Genius 15370 points
    Hi Bjoern,

    The WDT "divider" does not function the same way as a Timer divider does. These bits set the interval so the 33.57Hz frequency or 29.79ms is the correct interval as you've calculated above.

    Best regards,
    Caleb Overbay

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