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MSP430F67491: Trying to understand the clocking structure for the SD_24 data converter and DC spec the converter can achieve

Jeff Coletti
Expert 8645 points
Part Number: MSP430F67491

Hi Support team

I am a TI FAE (analog) and am working on a design where i need a smart  isolated ADC. I need to read 4 channels simultaneously, and need accurate DC specifications. So I am having trouble understand the clocking structure for FS, second, I am trying to see what type of performance I can get out of the data converters with a sampling rate of 1KHz, and third I need the DC performance, vos, drift, INL, DNL, 

Can you help me out with this?

Thanks

Jeff Coletti

  • 0
    TI__Guru**** 202336 points
    Hi Jeff,

    1. Please review Figure 29-2 of the User's Guide, fM = fMC = fSD24 so long as the SD24M4 bit is not set. Further divide settings are provided in SD24BCTL0 but the default SD24 frequency on device start-up will be 1048576 Hz.

    2. At the default fM you can use a SD24OSRx value of 1024 for the maximum conversion accuracy at a sampling rate of 1024 Hz. AC performance values for SD24OSRx values of 256 and 512 are recorded in the Datasheet with varying SD24GAIN values. You can also see SINAD vs OSR improvement in Figure 19.

    3. Most of these can be located in the datasheet, although perhaps not in the format you expect.

    Regards,
    Ryan

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