Compiler/MSP430F5632: Set MCLK With FLL

Hi Team
Please help us for this questions。
Thx

Hi,

I have started some work on this chip today too. Therefore not a lot of knowledge about it, and I wouldn't know to answer all your questions. However I can paste a copy of the function I use to set the XT2 oscillator. Slightly modified version to what's avalable in the resource explorer.
I had some trouble too, but seems to work now. My XT2 has a 20MHz crystal/18pF capacitor. Remember, for 24 MHz, you will need even more drive strength than mine. See the UCSCTL6 |= XT2DRIVE1; line in my code. You will probably need to put UCSCTL6 |= XT2DRIVE1 | XT2DRIVE0;.
I am typing as I am working on my code too. I still haven't tested the output with the oscilloscope on pin 3.4. I need to set up my hardware for that.


void Clock_init_xt2_20MHz(void)
{
P3DIR |= BIT4; // SMCLK to pin
P3SEL |= BIT4;

P7SEL |= BIT2 | BIT3; // Port select XT2

UCSCTL6 &= ~XT2OFF; // Enable XT2
UCSCTL3 |= SELREF__XT2CLK; // FLLref = REFO. Since LFXT1 is not used, sourcing FLL with LFXT1 can cause XT1OFFG flag to set
UCSCTL4 |= SELA__XT2CLK; //ACLK = REFO, SMCLK=DCO, MCLK-DCO

// loop until XT2, XT1, DCO settles
do
{
UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | XT1HFOFFG | DCOFFG); // Clear XT2, XT1, DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while(SFRIFG1&OFIFG); // test for oscillator flag fault

UCSCTL6 |= XT2DRIVE1; // XT2DRIVE bit15:14 '10'
// expected frequency
UCSCTL4 |= SELS__XT2CLK | SELM__XT2CLK; // SMCLK=MCLK=XT2

}

Hope this helps.

Kind regards,
Guyan

The datasheet says that when RSEL=7,DCO=31, then the actual DCO frequency might be anywhere between 60 MHz and 135 MHz. The DCO has lousy tolerances; this is why there is the FLL to adjust it to a target frequency.

The maximum allowed (S)MCLK frequency is 25 MHz.
It would be possible to run XT2 or the DCO faster, but to be able to use them as the clock source for MCLK, you would have to divide them down to a allowed frequency.

To get about 25 MHz, configure the FLL to run at 762 × XT1, and use a 32.768 kHz crystal. (The FLL does not run very well then the reference clock's frequency is near the target frequency.)
Alternatively, use a 25 MHz crystal on XT2, and use that directly as clock source (disable the DCO).

Hi Guyan and Clemens,

I know that there is not many knowledge about the clock system in the MSP430.
Now, my trouble is that, I have checked the route of the UCS Block Diagram and the registers in the datasheet of MSP430x5xx Family.
I have tried to use 24-MHz on XT2 and use 32768-Hz with FLL.
And no matter how I set, the clock from P3.4 (I set the SMCLK and CLK as DCOCLK) only around 5-MHz.
Maybe I am in a mess, but could you teach me how to check .

I use 32768-Hz on XT1, and I decided to use FLL to run with 25-MHz.
The code is changed from sample code,
while(BAKCTL & LOCKBAK)//Unlock XT1 pins for operation
BAKCTL &= ~(LOCKBAK);
UCSCTL6 &= ~(XT1OFF);//XT1 On
UCSCTL6 |= XCAP_3;//Internal load cap
do//Loop until XT1 fault flag is cleared
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG;//Clear fault flags
}while (SFRIFG1&OFIFG);//Test oscillator fault flag
__bis_SR_register(SCG0); //Disable the FLL control loop
UCSCTL0 = 0x0000; //Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_3;
UCSCTL2 = FLLD_1 + 761;
//(N + 1) * FLLRef = Fdco
//Set FLL Div = fDCOCLK/2
UCSCTL3 |= FLLREFDIV__4;
UCSCTL4 = SELM__DCOCLK + SELS__DCOCLK + SELA__XT1CLK;
__bic_SR_register(SCG0); //Enable the FLL control loop
__delay_cycles(76563); 
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG;//Clear fault flags
}while (SFRIFG1&OFIFG);//Test oscillator fault flag

Sincerely,
Norton

Start with the example code (msp430f66xx_UCS_07.c), and when you've got it to work, adjust as needed.