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MSP430FR4133: DCO set 6MHz with FLL

Hisao Uchikoshi
Genius 13880 points
Part Number: MSP430FR4133

Hello Experts,

I'm trying to set DCO to 6MHz with FLL but failed. I wrote below code.

        CSCTL1 |= DCORSEL_3;                    // Set DCO = 6MHz
        CSCTL2 = FLLD_0 + 182;                  // (182 + 1) * 32768 = 5.997MHz
        CSCTL0 |= DCO8;                          // set starting DCO tap is 256

In above case, CSCTL0,DCOx becomes all 0 while CSCTL0.DCOx becomes all 1 in case that  "CSCTL1 |= DCORSEL_2".

How can we set DCO to 6MHz appropriately?

Regards,

Hisao Uchikoshi

  • 0
    TI__Genius 13215 points

    Hi Hisao,

    I suggest you to configure the DCO as below processing which can be fond in the "3.2.11.1 DCO Factory Trim" of the device UG. You can take the code example msp430fr413x_CS_01.c as an reference.

    The recommended process to configure the FLL is:

    1. Disable the FLL.

    2. Select the reference clock.

    3. Clear the CSCTL0 register.

    4. Set the DCO range and set FLLN and FLLD for target frequency.

    5. Execute NOP three times to allow time for the settings to be applied.

    6. Enable the FLL.

    7. Poll the FLLUNLOCK bits until the FLL is locked.

    Even when the FLL is locked at a specific trim setting, large variations in temperature or prolonged shutdown of the FLL may result in the FLL unlock bit being set, which requires the execution of the software calibration and lock routine. Then you may need to do the software trim procedure described in "3.2.11.2 DCO Software Trim" of the UG. 

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