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MSP430FR4133: Is my ADC Reading variation normal

Part Number: MSP430FR4133

Hello,

I am currently trying to develop a Hall-sensing EVM with the MSP430FR4133.  At the moment I am trying to get stable ADC readings that I can use to display on an LCD display.  At the moment I seem to get a non-gaussian distribution of samples for a given input value.  Currently I am just using a battery (currently 1.62V) with a RC filter (1k, 10nF) leading to the channel A0.  The sample and hold is 256 cycles, ADCCLK = MODOSC, and the clock is divided by 8.  When I take 200 samples, I get the following distribution of ADC readings.  Would you expect to see this type of distribution in measurements with this particular microcontroller? The Bin values correspond to ADCMEM values. I expect roughly 502-503 for my voltage.

If you suspect layout is an issue.  Below is a snippit of my layout. C11 is the 10nF filter cap and C40 is the microcontroller's.  Currently the LCD is disabled and not utilized.  As of now, the other adjacent ADC channels are grounded.  Once this issue troubleshooted though, I intend to use each for a different hall sensor.  Top layer polygon pour is VCC and bottom polygon pour is GND.

  • BTW, for ADC measurement, I take about 100 samples. They are sorted, and average value of 8 mid samples is calculated.
  • Hello Patrick, zrno,

    Total unadjusted error is +/- 2 LSB for DVCC as reference, and variances of up to +/- 50 mV on the supply or sample input pin could result in the distribution recorded. Does the histogram already account for an average of the samples? Have different sample-and-hold times or clock configurations been attempted? And is there a possibility that the ADC39 errata could be involved?

    Regards,
    Ryan
  • Hey Ryan,

    Thanks for the information. The histogram was generated from raw un-averaged samples. If I average with 32+ samples the value actually converges to around the desired number or flickers between two adjacent numbers for a static voltage, due to relatively equal distribution of samples. However, my team believes that this is an issue, and I should get a Gaussian distribution. Previously I had lower sample-and-hold times as well as a faster clock or clock frequency divided by a smaller number. As for the ADC39 errata, are you suggesting I should enable the ADCSHP bit in the ADCCTL1 register? If so, I actually already have done that.

    Here is how I am currently setting up my ADC:
    // Configure ADC A0 pin
    SYSCFG2 |= ADCPCTL0;

    // Configure ADC10
    ADCCTL0 |= ADCSHT_8 | ADCON; // ADCON, S&H=16 ADC clks
    ADCCTL1 |= ADCSHP | ADCDIV_7; // ADCCLK = MODOSC; sampling timer
    ADCCTL2 |= ADCRES; // 10-bit conversion results
    ADCMCTL0 |= ADCINCH_0; // A0 ADC input select; Vref=AVCC
    ADCIE |= ADCIE0; // Enable ADC conv complete interrupt
  • Were results any different by changing sample-and-hold times or clock sources/dividers? Why divide MODOSC? What is your DVCC capacitance?

    Regards,
    Ryan
  • Hey Ryan,

    The results were pretty similar with the different sample and hold times and clock divisions. We thought a slower MODOSC would give the filter cap more time to recover from any transients induced by sampling or possibly external noise sources coupling to the trace. The DVCC capacitance is 1uF (16V rated) .
  • As stated in Section 5.3 of the datasheet, this should be at least 4.7 uF. We recommend 10 uF + 100 nF for proper decoupling.

    Regards,
    Ryan
  • Thanks Ryan,

    That actually fixed my problem.  As you can see in the distribution below.  There is a little offset, but I think I should be able to calibrate that out.

    Also just for anyone else that makes my mistake, if you look at the samples consecutively over time with the wrong bypass cap, you might get sinusoidal-like  readings like what I got below:

    Thanks Ryan again for the support!

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