MSP430F5329: More details in LPM3 and LPM4

Hi Kipton,
This is a subject of debate and is better determined experimentally. We haven't done a formal study to look into this.

You missed the other parts.

Is there another document on the low power modes besides the family module?

For example in my standby mode, I think I will be running using the VLO clock source 10000 Hz and ACLK will be at 1/32 of that or 312.5 Hz.

When I am not doing anything, I will go to LPM3.

Right now I am trying to figure out how to turn off the DCO since I use it in other modes, but not in this mode.

In the documentation for the family slau208p page 165 it says: "There may be scenarios in
which FLL operation is not required or desired; in these cases, no FLLREFCLK is necessary. This can be
accomplished by setting SELREF = {7}"

So going to page 464 of the MSP430F5xx_6xx Drivers Users Guide - 2_91_05_02 that is not an option for the driver.

In addition looking at figure 5-1 UCS Block Diagram on page 161 of the slau208p it shows that SCG0 turns off the 10-bit Frequency Integrator in the FLL. So when I am not using the FLL I need to make that bit 1 to lower power or just setting SELREF to 7 will do the same thing? Or are they different power levels?

I have not found if SCG0 affects anything else besides the FLL. So it is safe to leave it at 1 in this mode?

You guys drive me crazy.

So in the page 464 of the MSP430F5xx_6xx Drivers Users Guide - 2_91_05_02 they have UCS_CLOCK_SELECT all of the choices. This sets the SELREF bits in UCSCTL3 register.

So looking at the ucs.h it has:

#define UCS_XT1CLK_SELECT SELM__XT1CLK
#define UCS_VLOCLK_SELECT SELM__VLOCLK
#define UCS_REFOCLK_SELECT SELM__REFOCLK
#define UCS_DCOCLK_SELECT SELM__DCOCLK
#define UCS_DCOCLKDIV_SELECT SELM__DCOCLKDIV
#define UCS_XT2CLK_SELECT SELM__XT2CLK


So you are using the mapping for the SELM register for the SELREF register and hoping nobody makes a mistake.

Pretty sloppy but I understand what you are trying to do. You want one routine for all cases. Even though you are giving choices that do not exist and will not generate an error message if they are wrong.

Now I get to Table 5-6 UCSCTL3 Register Description in slau208p page 178.

Unlike page 165 it does NOT say that 7 is the same as off (see previous post in this thread). It says "111b = Reserved for future use. XT2CLK when available, otherwise REFOCLK"

The picture on page 161 Figure 5-1. UCS Block Diagram makes it look like 111b is not connected to anything.

So what is right?

Am I the only person who reads the documentation?

So I am blindly shooting at this. Can someone check my work. I do not know if the order is correct. I could not find any examples.




void CLK_Init2(void)
{
  uint16_t status;
  // I believe when everything is done the clocks are:
  // ACLK = 32768 Hz using REFO
  // MCLK = 8,192,000 Hz from REFO
  // SMCLK = 8,192,000 Hz from REFO
  // Set DCO FLL reference = REFO
  // Any external Crystals are off
  
  // probably coming from a lower level, so change CORE first.   
  
  PMM enableSvsLInLPMFastWake(); // Enables supervisor low side in LPM with 
                                  // twake-up-fast from LPM2, LPM3, and LPM4
  status = PMM setVCore(PMM_CORE_LEVEL_1);
  if (status == STATUS_FAIL) while(1); // we have problems. When debugging stop here. 
  
  PMM_enableSvsHSvmH();  // in this mode we have highside enable.
  PMM_enableSvsLSvmL();  // we need low side enabled in this mode.  
  PMM_enableSvsLReset(); // We should never see a low voltage event
  
  _BIC_SR(SCGO); // Make sure the FLL is turned on.
  UCS_turnOffXT1(); // Make sure external 32.768 kHz Crystal is off
  UCS_turnOffXT2(); // Make sure external 14.7456 MHz Crystal is off
  
  UCS_initClockSignal(UCS_FLLREF,
                      UCS_REFOCLK_SELECT,
                      UCS_CLOCK_DIVIDER_1 );
  // Set ACLK = REFO
  UCS_initClockSignal(UCS_ACLK,
                      UCS_REFOCLK_SELECT,
                      UCS_CLOCK_DIVIDER_1 );
  
  UCS_initClockSignal(UCS_SMCLK,
                      UCS_DCOCLKDIV_SELECT,
                      UCS_CLOCK_DIVIDER_1 );
  
  // Set Ratio and Desired MCLK Frequency and initialize DCO
  UCS_initFLLSettle(8192, // kHz
                    250 ); // 8192/32.768 = 250
  


  
  //Verify if the Clock settings are as expected
  clockValue[0] = UCS_getMCLK();
  clockValue[1] = UCS_getSMCLK();
  clockValue[2] = UCS_getACLK();
  return;
}

That is my fast clock and this is my standby clock

void CLK_InitStandby(void)
{
  uint16_t status;
  // I believe when everything is done the clocks are:
  // ACLK = 1250 Hz using VFO / 32
  // MCLK = 10000 Hz using VFO
  // SMCLK = 10000 Hz using VFO
  // Set DCO FLL reference = REFO
  // Any external Crystals are off

  // Set ACLK = VLO / 32
  UCS_initClockSignal(UCS_ACLK,
                      UCS_VLOCLK_SELECT,
                      UCS_CLOCK_DIVIDER_32 );
  // Set SMCLK = VLO -- this is used by I2C and UART which are disabled during sleep
/*  UCS_initClockSignal(UCS_SMCLK,
                      UCS_VLOCLK_SELECT,
                      UCS_CLOCK_DIVIDER_1 );
*/
  UCS_turnOffSMCLK(); // Turn it off since it is not used in this mode. 
  
  
  // Set MCLK = VLO
  UCS_initClockSignal(UCS_MCLK,
                      UCS_VLOCLK_SELECT,
                      UCS_CLOCK_DIVIDER_1 );
  
  // Make Sure the DCO is off
  UCS_initClockSignal(UCS_FLLREF,
                      SELREF_7, // NO code for 7 in library. 
                      UCS_CLOCK_DIVIDER_1 );
  
  
  
  UCS_turnOffXT1(); // Make sure external 32.768 kHz Crystal is off
  UCS_turnOffXT2(); // Make sure external 14.7456 MHz Crystal is off
  _BIS_SR(SCG0);    // Turn off the FLL to save power.
  
  // In this mode we are below 8 MHz so we can have PMMCOREV0 = 1.8V
  // so now that the frequency is lower we can set the voltage. 
  PMM_enableSvsLInLPMSlowWake(); // Enables supervisor low side in LPM with 
                                 // twake-up-slow from LPM2, LPM3, and LPM4
  status = PMM_setVCore(PMM_CORE_LEVEL_0);
  if (status == STATUS_FAIL) while(1); // we have problems. When debugging stop here. 
  
  PMM_disableSvsHSvmH(); // in this mode we never have highside so turn off to save power.
  PMM_enableSvsLSvmL();  // we need low side enabled in this mode.  
  PMM_enableSvsLReset(); // We should never see a low voltage event
  
  //Verify if the Clock settings are as expected
  clockValue[0] = UCS_getMCLK();
  clockValue[1] = UCS_getSMCLK();
  clockValue[2] = UCS_getACLK();
  return;
}

Am I close? Is anything in the wrong order? Is anything missing? 

Kip

Hi Kip,
My apologies, my reply was truncated last night. I meant for it to say I would look into WDT vs TimerA/B use. Indeed the WDT would be lower power to use.

I think the SELREF {7} confusion is coming from the Note on page 165 for MSP430F543x and MSP430F541x, non A versions, where they are wired to logic that will use XT2CLK or REFOCLK. But for your device, it would seem that this not connected this way. In either case, I would rely on the SCG0 bit to achieve lowest power when the FLL is not needed.

From your code, nothing jumps out at me as out of order or missing, provided no other modules are requesting any of the clocks you are turning off (which could cause the device to be in a higher LPM due to the request). Is it operating as expected?

There are DriverLib code examples available in TI Resource Explorer (file structure expanded at the following link: dev.ti.com/.../