MSP430F5329: Can I generate exactly 22118400 Hz from the REFO?

So 22118400 is a very convent number for a UART  

It also happens to be exactly 675 times 32768 Hz the frequency of REFO. 

When I try to use the UCS routines from the driverlib, I get 22085632 Hz which is exactly 32768 Hz away from my desired frequency according to UCS_getMCLK();

So my first thought was just change the divisor from 675 to 676 and that made it exactly -32768 Hz away. I thought the modulator was supposed to fix that kind of a problem.  

14745600 Hz seem to work and it is exactly 450 times 32768. 

It does not feel right. Am I missing something or doing something wrong here? Or is there some roundoff error in the utilities?

Here is my code: 

void CLK_InitFast(void)
{
  uint16_t status;
  // I believe when everything is done the clocks are:
  // ACLK = 32768 Hz using REFO
  // MCLK = 14,745,600 Hz from REFO
  // SMCLK = 7,372,800 Hz from REFO
  // Set DCO FLL reference = REFO
  // Any external Crystals are off
  
  if (pmm_get_core_level() < 3)
  {
    status = PMM_setVCore(PMM_CORE_LEVEL_3);
    if (status == STATUS_FAIL) while(1); // we have problems. When debugging stop here. 
  }
  
  PMM_enableSvsHSvmH(); // in this mode we have highside so turn on.
  PMM_enableSvsLSvmL(); // we need low side enabled in this mode.  
  PMM_enableSvsLReset();// We should never see a low voltage event
  
  UCS_turnOffXT1(); // Make sure external 32.768 kHz Crystal is off
  UCS_turnOffXT2(); // Make sure external 14.7456 MHz Crystal is off
  _BIC_SR(SCG0); // Make sure the FLL is turned on.
  
  UCS_initClockSignal(UCS_FLLREF,
                      UCS_REFOCLK_SELECT,
                      UCS_CLOCK_DIVIDER_1 );
  // Set ACLK = REFO
  UCS_initClockSignal(UCS_ACLK,
                      UCS_REFOCLK_SELECT,
                      UCS_CLOCK_DIVIDER_1 );
  
  UCS_initClockSignal(UCS_SMCLK,
                      UCS_DCOCLKDIV_SELECT,
                      UCS_CLOCK_DIVIDER_2 );
  
  //UCS_initFLLSettle(14745, // kHz
  //                  450 ); // 14745.6/32.768 = 450 -- gets 14745600 Hz
  
  UCS_initFLLSettle(22118, // kHz
                    675 ); // 22118.4/32.768 = 675 -- gets 22085632 Hz
 
  
  //Verify if the Clock settings are as expected
  clockValue[0] = UCS_getMCLK();
  clockValue[1] = UCS_getSMCLK();
  clockValue[2] = UCS_getACLK();
  return;
}