CCS: msp432 communited with cpld as spi slave recieve data error

uint8_t RXData = 0;


int main(void)
{
    WDT_A->CTL = WDT_A_CTL_PW |             // Stop watchdog timer
            WDT_A_CTL_HOLD;

    EUSCI_A1->IFG &= ~EUSCI_A_IFG_RXIFG;
    P2->SEL0 |= BIT0 | BIT1 | BIT3| BIT2;         // Set P1.5, P1.6, and P1.7 as
                                                  // SPI pins functionality

    CS->KEY = CS_KEY_VAL;                   // Unlock CS module for register access
    // Select ACLK = REFO, SMCLK = MCLK = DCO
    CS->CTL1 = CS_CTL1_SELA_2 | CS_CTL1_SELS_3 | CS_CTL1_SELM_3;
    CS->KEY = 0;                            // Lock CS module from unintended accesses

    CS->CTL0 = 0;
    CS->CTL0 = CS_CTL0_DCORSEL_3;                    //DCO
    CS->CTL1 = CS_CTL1_SELS_3 | CS_CTL1_DIVS_3;      // 12MHZ/8

    EUSCI_A1->CTLW0 |= EUSCI_A_CTLW0_SWRST;        // Put state machine in reset
    EUSCI_A1->CTLW0 = EUSCI_A_CTLW0_SWRST |        // Keep the state machine in reset
            EUSCI_A_CTLW0_SYNC |                   // Set as synchronous mode
            EUSCI_A_CTLW0_MSB |                    // MSB first and Slave
            EUSCI_A_CTLW0_MODE_2|
            EUSCI_A_CTLW0_STEM|
            EUSCI_A_CTLW0_SSEL__SMCLK;             // SMCLK

    EUSCI_A1->BRW = 0x02;                          // /3,fBitClock = fBRCLK/(UCBRx+1)=500KHZ.

    EUSCI_A1->CTLW0 &= ~EUSCI_A_CTLW0_CKPH;         //POLAR
    EUSCI_A1->CTLW0 &= ~EUSCI_A_CTLW0_CKPL;          //PHASE

    EUSCI_A1->CTLW0 &= ~EUSCI_A_CTLW0_SWRST;       // Initialize USCI state machine
    EUSCI_A1->IE |= EUSCI_A_IE_RXIE;               // Enable USCI_B0 RX interrupt

    // Remain in LPM on exit from ISR
    SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;

    // Ensures SLEEPONEXIT takes effect immediately
    __DSB();

    // Enable global interrupt
    __enable_irq();

    // Enable eUSCI_B0 interrupt in NVIC module
      NVIC->ISER[0] = 1 << ((EUSCIA1_IRQn) & 31);
}

// SPI interrupt service routine
void EUSCIA1_IRQHandler(void)
   {
      if (EUSCI_A1->IFG & EUSCI_A_IFG_RXIFG)
         {
        // received data
        RXData = EUSCI_A1->RXBUF;
         }
}