MSP432P401R: MSP432 low frequency crystal oscillator issue

Hello,

Do you have some PCBs which do not exhibit the fluctuation?  Is it possible to swap the crystal(s) to see if the issue remains with the CPU or Crystal?  Can you significantly change your application or run an example application to determine if there is any loading on the CPU that is impacting the crystal/oscillator performance?  When looking at P4.2 is there any indication that the noise fluctuation is periodic or does it look like thermal noise?

Regards,
Chris

Hi Chris,

Attached my answer.

Thanks,

Shlomi

MSP432P401.docx

Thank you for the information.  I will ask my colleague to also comment.  

Since the issue appears to stay with the CPU after swapping, I would like to focus on the configuration specifically the internal regulator and the RTC peripheral.  If you are using the DC-DC converter can you switch to the LDO.  Which Vcore are you using?  Low Power mode?  If you are not using the low power can you move away from the RTC and use the timerA to see if the issue is related to the RTC?

I did some power measurements and was able to see the RTC rollover in the power profile.  Not sure if this is impacting your setup but might be worth looking into.

Regards,

Chris 

Hi Chris,

I have configured the MSP to operate from LDO, using VCORE1 (since the CPU clock frequency is 48MHz), without entering any low power modes.  I haven’t noticed any changes in my fluctuation measurements.

Changing the RTC to TimerA is problematic at this stage. 

What did you mean by “RTC rollover in the power profile”? Can you elaborate on that? 

Thanks,

Shlomi

Hello,

    I received feedback from my colleague and his comment is that the LFXT is not intended to be accurate from cycle to cycle but to provide long term stability over a 1 second time frame.  With that said, since you do not see any changes when using the LDO and a consistent power mode, I am inclined to thing there is a different issue.  

    Regarding the RTC profile, I was wanting to see if the jitter was conicident with the Q7 found in the RTC registers RT0PS or RT1PS. 

Would your HW setup support running any of the basic examples?  If so, then perhaps I can put together a simple example with the timer to rule out the RTC.

Regards,
Chris

Hi Chris,

Attached my feedback.

Thanks,

Shlomi

MSP432.docx

Hi Chris,

I have done some more measurement of ACLK and RTCCLK and I keep seeing the same phenomenon:

Every once in a while an RTCCLK cycle deviates by ~30us, but nothing unusual is observed on the ACLK. Since they are both sourced from the LFXT this should lead to the conclusion that the RTC is at fault. However, RTCCLK looks good when the crystal is replaced with an external oscillator, which leads to the conclusion that the crystal is to blame and not the RTC. 

How can this be explained? Perhaps the ACLK has some extra filtering in its path which make it less susceptible to crystal noise? Is it possible that a faulty LFXT clock will cause issues with RTCCLK but not with ACLK? 

Any help on the matter will be appreciated,

Thanks,

Shlomi

Hello,

    I do not have any good leads at this time.  The RTC is fed through BCLK without any divider while ACLK has a divider after the mux.  When you use the TCXO is the LFXT in bypass mode?  

    I will need to confirm, but typically there is a startup filter that counts the number of valid pulses before the LFXT signal is sourced to the system clocks (ACLK, SMCLK, etc).  I do not know if BCLK is considered part of the system clocks or a specific clock for the RTC.  If a different filter where applied, then I would only expect you to see issues at startup.  

    This is a lot of great information an feedback that I can provide to the team to further investigate the differences between ACLK and BCLK.

Regards,

Chris

Hi Chris,

I have some more findings after performing tests on a sample of 40 PCBs:

§  The issue occurs in ~12% of the PCBs.

§  In some PCBs the clock can fluctuate both ways. I.e. 1sec as measured by the RTC can last 1s+30µsec or 1s-30µsec.

§  Unlike stated previously, low power mode does have an effect:

On some PCBs, when the MSP432 remains in active mode and does not enter LPM3, the observed RTC fluctuations are less frequent.

Note that the problem is still there, however it is not as prominent.

Can the switching between different power modes cause disruptions on the RTC clock?

Have you had any luck with reproducing the issue?

Thanks,

Shlomi

Hi Chris,

Did you available for a conference call to discussing the issues? You can send me mail to shlomi@telsys.co.il

Thanks,

Shlomi

Hi Chris,

Any update?

Thanks,

Shlomi

Shlomi,

    Can you confirm when using the TCXO that the LFXT oscillator is not in bypass mode (LFXTBYPASS = 0)?  Are you using the RTC offset calibration, which removes or adds a clock every quarter second? 

Is there an RTCOIFG at any time during the operation, either through the entering/exiting of LPM, or just during operation?  Specifically, is the RTCOFIFG without and LFXTIFG?

Thanks,
Chris

Chris Hello,

Shlomi is OOO for vacation, so I'll continue the correspondence, please find the customer response below:

1.       When using the external TCXO we purposely set the LFXT to bypass mode (LFXTBYPASS = 1). Shouldn’t we?

2.       We are not using RTC offset calibration.

3.       The RTCOFIFG is not set at any time (always ‘0’). 

Please advise back, thanks in advance

Shai

correspondence

Hello,

Thank you for the additional information.

Yes, the LFXT should be in bypass mode when using with the TCXO. Since you are not using offset calibration
and not seeing faults, I do not think there is a setup issue.

The MSP432P401R datasheet does not include any parameters regarding the LFXT performance except to list
criteria about the input requirements of the crystal and the power performance. This means I cannot request
additional resources to help with this case. I can only provide suggestions which I believe might help but
cannot guarantee any performance outside of the datasheet.

Other considerations:
Shlomi mentioned in a previous email that experiments were conducted to increase the pybass capacitance on
AVCC, but since there is now evidence that low power mode switching has an impact, I would recommend revisiting
this and including the DVCC rail.

Is the REFO clock source acceptable in terms of tolerance and immune to the bursts you are
seeing?

Regards,
Chris

Hi Chris,

Unfortunately the issue remains unsolved.

Perhaps there is some correlation to AVCC/DVCC decoupling but increasing bypass capacitance doesn’t solve the issue.

Using the REFO is not an option since we require at least 10ppm frequency tolerance.

Currently, our only option is to use an external oscillator.

I think it may be helpful if TI tries to reproduce the problem. As described previously, we observed the clock fluctuations by simply sampling the RTCCLK output.  

The problem is observed on approximately 12% of our boards. 

Thanks,

Shlomi