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MSP430F448 quartz correction

fekete.laszlo
Prodigy 10 points
Other Parts Discussed in Thread: MSP430F448

Dear All!

 

I meet the MSP430F448 now.

I beginner in the them.

Can you help me?

 

How to do it in C source program, the following task?

( I need use the process in command line.)

We have  MSP430 GANG programmer. 

 Quartz correction

1st step : take out the ACLK through the JTAG (P1.5) to measure the frequency F_ACLK. : this value will be the base for the calculation. Once this is done, one must calculate and flash the corrective values To measure frequency we use a universal frequency counter AGILENT 53132 with option 010 Highstability timebase.

Processor register coding by JTAG :

a/FLL programmation:

SCFI0 Configuration => SCFI0 = 0x10

SCFQCTL Configuration => SCFQCTL = 0xFF

FLL_CTL0 Configuration => FLL_CTL0 = 0x31 b/ ACLK output Programmation:

Periphery function of P1.5 selected => BIT5 of P1SEL position

P1.5 in output => BIT5 of P1DIR position ACLK measurement use in the tester:

• If the accuracy of the quartz frequency is above 50ppm from the theoretical 32768:

• The PCBA is to be rejected. Frequency > 32770 OR <32766 • If 32767,5 Hz • quartz frequency • 32768,5 Hz

• No quartz calibration. (Frequency is OK).

• If not, the tester should calibrate the quartz.

Correction of the time drift:

The calculation of the time drift is the following:

(F_ACLK in Hz, measured value)

Then flash ACLK correction : The round up of the absolute value from the correction at the address 0xFFDA-0xFFDB (the value is on 2 bits) And the sign at the address 0xFFDC : if the sign is +, record 0x01 if not record 0x00.

• after loading binary software (see below paragraph 2) Master clock MCLK correction:

In order to have a master clock (MCLK) at 4,194304 MHz, the following calculation is needed:

(F_MCLK in Hz, measured value)

Round up at the unit in order to put it in one bit.

 

Flash Master clock correction N at 0xFFD6 address

 

Thank you for your help in advance.

  • 0
    Guru 227245 points

    It's not a direct answer to your question, bu tperhaps a solution for the underlying problem:

    Usually, the influence of the load capacitance of a clock crystal is larger than the crystals tolerance. So maybe an adjustable capacitor ont he crystal will deliver better results than any software solution. At least for the initial precision. I didn't do it on an MSP, bu tfor our devices, we sometimes use an external I2C-connected realtime clock which also uses a 32kHz crystal. There I add an adjustable capacitor to the load capacitors (for the MSP: lower the internal cap setting). The RTC will output a 1s pulse signal, but if on the MSP you route the incomung 32kHz signal to ACLK and then to an output pin, it servers as well. This signal is measurted by a high-precision counter/timer. And it is soimple to adjust the capacitor until the displays shows 1.000000s (or in your case 32768.0Hz). I get the base accuracy easily trimmed to <10ppm which is 32768+-0.4hz. or (in case of the RTC) <0.5s/day.

    If you're checking the frequency through the gang programmer, keep an eye on this devices precision. It might turn out to have a higher tolerance than your whole calibration process. (I don't know the specs).

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