MSP430FR2311: ADC timing question

Hello Ajayt,

I am sorry, but you need to provide way more details on your implementation and code, to enable us giving you a meaningful answer.

But before I start listing the things, we need, and you/your customer needs to consider, one additional question from me on the expectation, that by using the eComp, the sampling and conversion of the ADC should be triggered automatically. Please see Figure 21-1 from the User's Guide, which shows the block diagram of the ADC. Unless I've overlooked something, there is no path to the output signal of the eComp. The only available triggers to start a sampling&conversion activity of the ADC, are either ADCSC (which is SW), or three different Timer triggers. So maybe you could elaborate on this topic in more detail.

Now to the additional information and considerations one need to make, when looking at the scope plot you've provided.

1. We need to know the system clock frequency. As your executing multiple things by the CPU, we need to know the CPU clock to be able to calculate back the execution time, related to those.

- You're processing the eComp ISR triggering the ADC

- You're processing the ADC ISR, toggling the GPIO, which you're trying to use to estimate the time point of the sampling.

2. What operating mode are you using? Are you in an LPM, when the eComp interrupt occurs? Then you would need to consider the startup time of the system and clocks.

3. What operating mode of the eComp are you using. The scope plot shows the input signal of the eComp, but not the output. But not the input is triggering the eComp ISR, it is its output. Dependent on the operating mode, there is a delay between eComp input and output.

4. The entire calculation of the timings for the whole sequence you're running is missing. If you think the timing should look different, I would expect an explanation and justification based on calculation of the timings. Some of them mentioned in my previous points. The 200kSps specification just states, if the ADC is running at full speed, with back to back sampling and conversion, you can reach 200kSps. But you're far away from the highest speed due to all the delays, you're building in. Thus need to calculate them. If then a mismatch between the calculation and reality will be the outcome, then we can start looking into why it is the case. But so far I have not seen anything contradicting the specified functionality and performance.

Best regards

Peter

Hello Ajayt,

I assume your question has been answered sufficiently, thus I am closing the thread.

Best regards

Peter

HI Peter, 

To answer the questions below, I’ve attached a copy of my eComp registers when entering the ISR. Sysclock = 8MHz, Operating mode is LPM0. On my timings, I have some control over my sample window which is currently ~30 usec. I would be looking to sample at the mid-point by using extended sampling mode and extending SHI accordingly.

Hope that helps, please let me know if you need any more information and I would appreciate any suggestions to improve timings

attached is the codeTo answer the questions below.docx

1) With CONSEQ=0 and SHS>0, your ISR needs to toggle ENC (low then high) between conversions. The symptom is that you get one conversion but no more. [Ref User Guide (SLAU445I) Fig 21-11].

2) I see you have CPIE enabled. With CPIES=1, this would presumably trigger CPIFG (falling) along with starting the ADC. How long does your ECOMP0_VECTOR take to run?

3) It might be useful to capture the actual COUT signal on P2.0 on the scope, rather than supposing when it happens. [Ref data sheet (SLASE58C) Table 6-44.]