CCS/MSP430FR69721: Appropriate sample hold time at ADC12

user4750242

Prodigy 80 points

Part Number: MSP430FR69721

Tool/software: Code Composer Studio

Hi,

Calculation method of the minimum sampling time tsample is as follows.

If Rs is greater than 10kΩ, can I use tsample as the result of this calculation?

Also, for example , assuming tsample is 4nsec, one clock cycle is 1nsec , is ADC12SHT right for 0000b?

over 4 years ago

0 Winter Yu over 4 years ago

TI__Genius 12315 points

Hello,

No, it's not recommended that a signal source has very high resistance. If the signal source resistant is high, you should add a OPA as follower to reduce resistant.

Yes, the 0000b is 4 ADC12CLK cycles.

But one exception is for the first conversion or where ADC12MSC=0 where an extra 3 ADC12_B source clock cycles is required when SAMPCON goes high. (see UG Figure 34-5 and Figure 34-6).

Please set ADC12SHT to 0001b (8 cycles) for the exception.

0 user4750242 over 4 years ago in reply to Winter Yu

Prodigy 80 points

Hi,

Thanks for the reply.

Is it not recommended that a signal source has very high resistance because it reduces measurement accuracy?

Also,can high source resistance lead to MCU failure?

Best regards.

0 Winter Yu over 4 years ago in reply to user4750242

TI__Genius 12315 points

Yes, it reduces measurement accuracy. High source resistance won't lead to MCU failure.

0 user4750242 over 4 years ago in reply to Winter Yu

Prodigy 80 points

Thanks for the response.

All problems have been resolved.

Thank you!

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CCS/MSP430FR69721: Appropriate sample hold time at ADC12