Hi All,
In configuring a software delay with delay_cycles, I was looking at the generated source of CAPT_BSP.c and saw this:
//*****************************************************************************
// CAPT_BSP.c
//
// *** CLOCK CONFIGURATION ***
// MCLK is 8 MHz, sourced from the DCO
// SMCLK is 2 MHz, sourced from MCLK
// ACLK is 32kHz, sourced from XT1 or REFO, with XT1 having priority
// FLLREF is 32kHz, sourced from XT1 or REFO, with XT1 having priority
//
However, in CAPT_BSP.h:
#define MCLK_FREQ (16000000)
So two questions:
1) Is 8MHz a recommended clock for applications using the captivate technologies?
2) How is it getting set to 8? Where? Can/should it be configured?
I am new to MSP 430 so I hope this isn't a terrible obvious thing I am overlooking. I was looking into the DCO register configuration but figured I should ask here as well.