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MSP430FR5962: ADC Repeated Autoscan Issues

Part Number: MSP430FR5962

Hello all,

I'm trying to use the repeated autoscan mode on the MSP430FR5962. I'm having a few issues getting the feature working. After all of my attempts I have not been able to get the module to work correctly. Sometimes the repeated function will work and sometimes it will not. I have a feeling I'm not setting up my registers correctly.

Here's my current ADC setup code.

    //P1.2 - A2 - Pin 3
    P1SEL0 |= BIT2;
    P1SEL1 |= BIT2;

    //P1.3 - A3 - Pin 16
    P1SEL0 |= BIT3;
    P1SEL1 |= BIT3;

    // Configure ADC12
    ADC12CTL0 = ADC12SHT0_2 | ADC12ON | ADC12MSC;       //16 clock cycles sampling, ADC on, multiple sample.
    ADC12CTL1 = ADC12SHP | ADC12SSEL_3 | ADC12CONSEQ_3; //Pulse mode. ADCCLK = SMCLK. repeated autoscan.
    ADC12CTL2 = ADC12RES_0;         //8-bit conversion results

    // Configure ADC input channels
    ADC12MCTL1 = ADC12INCH_2 | ADC12VRSEL_0;   //A2 ADC input select; Vref=VCC=3.3V
    ADC12MCTL2 = ADC12INCH_3 | ADC12VRSEL_0 | ADC12EOS;   //A3 ADC input select; Vref=VCC; End-of-sequence

    ADC12CTL0 |= ADC12ENC | ADC12SC;

Here is my ADC ISR code:

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = ADC12_B_VECTOR
__interrupt void ADC12_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_B_VECTOR))) ADC12_ISR (void)
#error Compiler not supported!
   switch (__even_in_range(ADC12IV, ADC12IV__ADC12RDYIFG))
        case ADC12IV__NONE:        break;   // Vector  0:  No interrupt
        case ADC12IV__ADC12OVIFG:  break;   // Vector  2:  ADC12MEMx Overflow
        case ADC12IV__ADC12TOVIFG: break;   // Vector  4:  Conversion time overflow
        case ADC12IV__ADC12HIIFG:  break;   // Vector  6:  ADC12BHI
        case ADC12IV__ADC12LOIFG:  break;   // Vector  8:  ADC12BLO
        case ADC12IV__ADC12INIFG:  break;   // Vector 10:  ADC12BIN
        case ADC12IV__ADC12IFG0:   break;   // Vector 12:  ADC12MEM0
        case ADC12IV__ADC12IFG1:
            var1 = ADC12MEM0;
        break;   // Vector 14:  ADC12MEM1
        case ADC12IV__ADC12IFG2:
            var2 = ADC12MEM1;
        break;   // Vector 16:  ADC12MEM2
        case ADC12IV__ADC12IFG3:   break;   // Vector 18:  ADC12MEM3
        case ADC12IV__ADC12IFG4:   break;   // Vector 20:  ADC12MEM4
        case ADC12IV__ADC12IFG5:   break;   // Vector 22:  ADC12MEM5
        case ADC12IV__ADC12IFG6:   break;   // Vector 24:  ADC12MEM6
        case ADC12IV__ADC12IFG7:   break;   // Vector 26:  ADC12MEM7
        case ADC12IV__ADC12IFG8:   break;   // Vector 28:  ADC12MEM8
        case ADC12IV__ADC12IFG9:   break;   // Vector 30:  ADC12MEM9
        case ADC12IV__ADC12IFG10:  break;   // Vector 32:  ADC12MEM10
        case ADC12IV__ADC12IFG11:  break;   // Vector 34:  ADC12MEM11
        case ADC12IV__ADC12IFG12:  break;   // Vector 36:  ADC12MEM12
        case ADC12IV__ADC12IFG13:  break;   // Vector 38:  ADC12MEM13
        case ADC12IV__ADC12IFG14:  break;   // Vector 40:  ADC12MEM14
        case ADC12IV__ADC12IFG15:  break;   // Vector 42:  ADC12MEM15
        case ADC12IV__ADC12IFG16:  break;   // Vector 44:  ADC12MEM16
        case ADC12IV__ADC12IFG17:  break;   // Vector 46:  ADC12MEM17
        case ADC12IV__ADC12IFG18:  break;   // Vector 48:  ADC12MEM18
        case ADC12IV__ADC12IFG19:  break;   // Vector 50:  ADC12MEM19
        case ADC12IV__ADC12IFG20:  break;   // Vector 52:  ADC12MEM20
        case ADC12IV__ADC12IFG21:  break;   // Vector 54:  ADC12MEM21
        case ADC12IV__ADC12IFG22:  break;   // Vector 56:  ADC12MEM22
        case ADC12IV__ADC12IFG23:  break;   // Vector 58:  ADC12MEM23
        case ADC12IV__ADC12IFG24:  break;   // Vector 60:  ADC12MEM24
        case ADC12IV__ADC12IFG25:  break;   // Vector 62:  ADC12MEM25
        case ADC12IV__ADC12IFG26:  break;   // Vector 64:  ADC12MEM26
        case ADC12IV__ADC12IFG27:  break;   // Vector 66:  ADC12MEM27
        case ADC12IV__ADC12IFG28:  break;   // Vector 68:  ADC12MEM28
        case ADC12IV__ADC12IFG29:  break;   // Vector 70:  ADC12MEM29
        case ADC12IV__ADC12IFG30:  break;   // Vector 72:  ADC12MEM30
        case ADC12IV__ADC12IFG31:  break;   // Vector 74:  ADC12MEM31
        case ADC12IV__ADC12RDYIFG: break;   // Vector 76:  ADC12RDY
        default: break;

var1 and var2 from the ISR are the values I'm trying to output. They either don't change during repeated autoscan or show completely random, changing values. 

I've read the datasheet chapter on the ADC a few times over now and I can't seem to fix the issue.

Does anyone know what I'm doing wrong? 


    This starts with ADC12MCTL2, which is (also) the end of the sequence, so you'll just do that one (ADC12INCH_3) over and over. Try:

    > ADC12CTL3 = ADC12CSTARTADD_1;    // ADC12MCTL1, then 2


     >       case ADC12IV__ADC12IFG1:
     >           var1 = ADC12MEM0;

    IFG1 applies to ADC12MCTL1, so you should fetch from ADC12MEM1. The two following lines should fetch from ADC12MEM2.


    I don't see where you set any of the IE bits. For this code, you should enable ADC12IE1 and ADC12IE2. An alternative strategy is to enable only ADC12IE2 and fetch both MEM1 and MEM2 on IFG2.


    Unsolicited: You're using ADC12SSEL=3=SMCLK, which doesn't run in the lower Low Power Modes (LPMs). I usually find MODOSC (ADC12SSEL=0) to be plenty fast, and it runs whenever I need it.