MSP430F5418A: Migrated code from IAR to CCS - timing issues...

Thanks Aaron.

I went back to some of the sample programs using the UCS specifically msp430x54x_UCS_9.c and i realized that there were some settings that were missing. (Maybe in IAR they weren't needed? default?)

Now the code is working perfectly - here it is below (changed to TIMERB0):

#define TIMEDIVISION    16128   /* for time interrupt settings: 1 msec period - 16.128 Mhz clock.*/

/*******************************************************************\
 timehandler( ): The time interrupt handler. 1msec interrupt module
\*******************************************************************/
#pragma vector=TIMER0_B0_VECTOR
__interrupt void timehandler(void)
{
  isRAM_TestInterruptReported = 1; // Indicate to the RAM test that an interrupt was called.

  // Update the time
  tik += 1;
  msec++; // Update the milli-second counter

  if (tik >= 1000)  // Does the seconds counter needs to be updated?
  {
    sec++; // Update the seconds counter.
    tik -= 1000;
  }
  
  if (msec & 0x01)  // for scope
  {
      P2OUT |= 0x01;  // toggle each tik
  }
  else
  {
      P2OUT &= ~0x01;  // toggle each tik
  }

  TB0CCR0 += TIMEDIVISION; // Add offset to CCR0 (Compare Register)
} /* of timehandler */




/***************************************************\
 * InitTimer : Initializes timer.		   *
\****************************************************/
void InitTimer()
{
  
  P7SEL |= 0x03;                            // Port select XT1
  UCSCTL3 |= SELREF_2;                      // FLL Ref = REFO
  UCSCTL6 &= ~XT1OFF;                       // Set XT1 On
  UCSCTL6 |= XT1DRIVE_3 + XTS;              // Max drive strength, for start. Enable XT1 in High Freq mode. 
                                            

  // Loop until XT1,XT2 & DCO stabilizes
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

  //UCSCTL6 &= ~XT1DRIVE_2;                     // Drive strength reduces.
  
  UCSCTL4 = SELA__XT1CLK + SELS__XT1CLK + SELM__XT1CLK; // Select Aclkm Mclk and Smclk from Xt1.

  UCSCTL5 = DIVS_5;  // Divide  SMCLK by 32 , SMCLK is used for watchdog.- 65 ms interval.
 

  // Initialize timer B0
  TB0CTL = TASSEL_1 + MC_2;   // 0x120 ACLK, Continuous up
  TB0CCTL0 = CCIE;              // CCR0 (Compare Control Register) interrupt enabled
  TB0CCR0 = TIMEDIVISION;	      // Set the first time the timer interrupt is called
  
  sec = 0;
  msec = 0;
  tik = 0;		
} /* of InitTimer */