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I have a custom board, running an MSP430F47183. When I measure the MCLK pin with a scope, it shows the frequency to fluctuate anywhere between 33 MHz and 37 MHz. Is this reasonable? And is there a way I can make this slightly more accurate? I'm still in the process of understanding FLL, so I may have some more questions on that later. But what can I expect for clock jitter? I have an external 32 kHz clock sourcing MCLK.
This is my clock setup:
SCFI0 = FN_4 | FLLD1 | FLLD_8; // FN_2 (1.3 to 12.1 MHz); D = 2 //SCFI0 = FN_2 | FLLD1 | FLLD_1; FLL_CTL0 = DCOPLUS | XCAP0PF; // DCO+ set, fDCOCLK = D x (N + 1) x fACLK, 0pF FLL_CTL1 &= ~SELS; SCFQCTL = 127; SCFQCTL |= 0x80;
Well you set the following things in your code snippet:
Use FN_4 which results in a possible DCO range of 2.1 MHz to 41 MHz (this is the maximum range for 3 volts). You divide the ACLK by 8 (note that setting FLLD1 | FLLD_8 is confusing). You select a not divided DCO output for MCLK/SMCLK (DCO+). Then you use a multiplier of 127 and turn of the modulation pattern (SCFQCTL |= 0x80;).
Now that results in 8*(127+1)*32768Hz = 33.55 MHz. Theoretically that is. The FLL will now select the DCO tap which will give you the nearest frequency to that. As you turned off the modulation pattern the frequency should be quite stable.
BUT you are using your device outside the specifications. The MCLK and SMCLK are specified to a maximum of 16MHz. The pins are specified to output at maximum 16MHz (at 3 volts and without load).
That being said there are also other things which might influence the performance, the DCO is quite voltage dependent and if you supply the MSP with a switchmode power supply the voltage ripple will transform into a frequency ripple.
Just a bit explanation of the FLL: Normally the modulation pattern of the FLL is active and then the FLL will switch between different DCO taps to get an average frequency as close to the set frequency (so normally it will toggle between two adjacent taps). Now the DCO taps are up to 17% of frequency apart. So you will see a varying DCO frequency at the output - and considering this modulation between two taps you can see that a change from 33MHz to 37MHz is quite possible (12% change).
Now what makes me wonder a bit is, that you turned the modulation of, but maybe it still tries to get the closest tap to the frequency selected so it still changes the tap but just not as often as it would with modulation. (I'm not sure about that part in the 4xx FLL loop)
You can turn of the FLL loop completely through setting SCG0 in the status register (_bis_SR_register(SCG0);) then the DCO runs at the selected tap and you shouldn't see the frequency changes anymore.
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In reply to Bernhard Weller:
Bernhard WellerNormally the modulation pattern of the FLL is active
The modulation is part of the DCO and independent of the FLL.Two DCO taps are 7 to 17% (2 to 12% on 5x devices, which too have almos tthe same FLL) apart and chances are that none of the possible , jitter-free DCO TAP settings will match your desired frequency.So modulation is used to switch between DCOx and DCOx+1 based on a configuratble patter which increses from no modulation to n/32 of one and (32-n)/32 of the next higher tap.
The FLL increases both, the modulation first, and then the DCO tap selection.
If you disable modulation, the FLL has no choice but to increase or decrease the tap selection itself, causing the DCO to run (worst case) 8% too low for one and 9% too high for the next FLL adjustment cycle (which depends on the reference clock).
So disabling modulation makes things worse. It eliminates the jitter between individual clock cycles by introducing larger frequency shifts over a larger time. The FLL can no longer adjust teh modulation for small adjustments, it can only switch between DOC taps now and does so, with the observed results.
One way to reduce the jitter is to leave modulation on, but use a higher DCO frequency. e.g. for 16MHz MCLK/SMCLK, set the DCO for 32MHz and just a /2 divider. This reduces the modulation jitter, since two DCO clock cycles are combined into one. Best case, if the target frequency is in the middle of two taps, it will be jitter-free then (the modulation wil get one cycle here, one cycle there, and the average of two is constant). For all other modulation settings, the maximum jitter will be half as much as before. (for 8MHz you can get 1/4 jitter with 32MHz DCO and /4 divider)
Time to say goodbye - I don't have the time anymore to read and answer forum posts. See my bio for details.Before posting bug reports or ask for help, do at least quick scan over this article. It applies to any kind of problem reporting. On any forum. And/or look here.I'm sorry that I can no longer provide help in the forum or by private conversation.
In reply to Jens-Michael Gross:
Thanks for the help guys. That really explained a lot. I've dropped the clock down to 16 MHz, and that solves a lot of my problems, not just clock stabilization.
Really apprecaite it.
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