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MSP432P4111: BSL startup failure

Chris Schmitzer
Prodigy 30 points

Part Number: MSP432P4111

There is exhaustive documentation how to utilize and/or change the resident bootloader (BSL) on the device by branching to 0x20200 (see e.g. https://www.ti.com/tool/MSPBSL).

However, what if such calls fail to produce the expected response?
BSL does a complete system setup of its own, including the clock system and interrupt vectors.
But after much trial and error, I have discovered two issues, which are absolutely deadly with respect to BSL invocation.

    1. if there is previous unfinished output pending in EUSCI_A0 (loading TXREG and not waiting for output completely serialized onto the TXline), even disabling the module (prematurely) will leave something in a volatile state, incompatible with BSL startup
    2. initially using SYSTICK services without disabling the module and associated interrupts also is inpalatable for BSL startup.

After introducing a forced delay to allow any characters to leave the TX shift register and disabling the SYSTICK module, BSL will startup ok.

;-)

  • 0
    TI__Genius 12315 points

    Hi Chris,

    Thanks for your sharing. Your findings are correct and very useful.

  • 0
    Prodigy 30 points

    UPDATE:

    After some more work, here are DOs and DONTs:

    DO enter the BSL by means of a coded hard reset of your device, i.e. use the feature of a unique code for hard reset, and in your boot routine, jump to BSL if you recognize the code immediately upon entry. This takes care of all peripheral resets.

    DONT use any port mapping. You may use any ports available, however interrupt redirection (by means of 'registerInterrupt') and reduced clock rate cause unacceptable delays at most UART baudrates.

    Observing these hard-won relevations makes BSL run smoothly.

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