Hi,
The question about MSP430 input ADC impedance shows up quite frequently in this forum. I looked through many responses. The answer is that this is a statistical impedance, and suggestion to look into paragraph 21.2.5.3 Sample Timing Considerations (for MSP430FR2xx family). Which shows how select proper timing for sampling. It looks like the input of ADC is resistance of multiplexor, around 4k and an Internal capacitor to hold the sampled voltage. From the picture the capacitor is always connected via MUX resistor to the input and RC chain defines the impedance. If capacitance is very low there will be no effect on the input, if it is very high it will short input signal; those might be two extremes. The whole consideration for timing is to provide enough time to allow the capacitor to charge taking into consideration external source Rs impedance. I have voltage clamping when ADC is connected to the output of my voltage divider and I cannot explain why is clamping happening based on the available info in manuals. Clamping is nonlinear problem. Rs is approximately 60 kOm. Oscilloscope screenshots show voltage with and without ADC input connected.
I appreciate your help!
