Hello.
In our project we are facing following problem ...
There's running long term test with 14 pieces of our device (TIVA controller). These devices are connected to one power supply, which is cyclically turned off and on for 3 seconds. After each restart there's checked the state of all the devices (they have to start to properly communicate with PLC via Profinet) and if all of them are ok the power supply is turned off and on again. After several hundreds of restarts of the system (which means thousands of restarts of devices, because 14 devices are restarted every time), one of the devices (a different piece every time) gets to a very strange state, it's somehow slowered down. It seems to be approx. 15 times slower, startup is longer, LEDs blinking is slower, responses on ethernet bus (Profinet) is slower. It seems to be a problem with clock frequency.
We set the clock frequency in the following way ...
uint32_t realFrequency = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), 120000000); //120 MHz
and checking the return value that it was se properly. There's returned the required value of 120000000 every time even in the problematic cycle of the device.
When I set 8 MHz instead of 120 MHz ...
MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), 8000000); //8MHz
then the device behavior is similar to the issue which can be seen in our long term test.
I was reading the err data document and I found there the error SYSCTL#22 Change to the PLL Clock Divider may Cause System Clock to be out of Specification.
I thought that it could also be our problem but then I found out that we're using TivaWare_C_Series-2.1.4.178_drl and it should contain the fix for that error.
My questions ...
1) Don't you have any explanation for that issue? Aren't there any other "frequency" problems in the controller which could cause similar behavior?
2) When the problem described in SYSCTL#22 occurs, what's the result, what does it mean that "cause the system clock to be out of specification"? Which frequency is set? Could it cause similar behavior as in case of our device?
3) How could I verify that the 120MHz frequncy was really set properly? Could you me provide a piece of code how to handle it, please?
Thank you in advance for any help.
Zdenek Krejsa