Other Parts Discussed in Thread: EK-TM4C1294XL
Hi Experts
My customer is having issues with the ADC results on the device, details are below:
We recently switched reference voltages from an external regulator to the internal reference on the above Tiva. We are now seeing values of 2.97V when we sample ADC channels, at most. We know from the datasheet that there is a voltage drop when using internal, but it doesn’t cite how much of a voltage drop. Is a 0.3V drop reasonable?
I asked for the following information:
- What are the voltages on VDDA and VDD at the IC?
- What is the highest Vin you have applied to the ADC inputs?
- Is the ADC configured for single ended operation or differential?
- What ADC sample rate are you operating at?
Here is the customer response:
"VDDA and VDD are both at 3.32V. Responses to other questions from our SW guy:
Using differential, sample rate is full. Below are the TI API calls:
ADC_CTL_D selects diffential.
MAP_ADCSequenceStepConfigure (ADC0_BASE, SAMPLE_SEQ_NUM, 0,
ADC_CTL_CH0 | ADC_CTL_D | ADC_CTL_IE | ADC_CTL_END);
ADC_CLOCK_RATE_FULL means sample at full rate.
ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_FULL, 1);
There’s also an oversampling rate. We use the highest, which is 64.
MAP_ADCHardwareOversampleConfigure( ADC0_BASE, 64 );
"
Please let me know if you have any recommendations to debug this issue further.
Best regards,
Jim B