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TM4C129ENCPDT: ADC conversion values incorrect after switching to internal reference

Jim Brinkhurst1
Mastermind 44440 points
Part Number: TM4C129ENCPDT
Other Parts Discussed in Thread: EK-TM4C1294XL

Hi Experts

My customer is having issues with the ADC results on the device, details are below:

We recently switched reference voltages from an external regulator to the internal reference on the above Tiva.  We are now seeing values of 2.97V when we sample ADC channels, at most.  We know from the datasheet that there is a voltage drop when using internal, but it doesn’t cite how much of a voltage drop.  Is a 0.3V drop reasonable?

I asked for the following information: 

  • What are the voltages on VDDA and VDD at the IC?
  • What is the highest Vin you have applied to the ADC inputs?
  • Is the ADC configured for single ended operation or differential?
  • What ADC sample rate are you operating at?

Here is the customer response:

"VDDA and VDD are both at 3.32V.  Responses to other questions from our SW guy:

Using differential, sample rate is full. Below are the TI API calls:

ADC_CTL_D selects diffential.

  MAP_ADCSequenceStepConfigure (ADC0_BASE, SAMPLE_SEQ_NUM, 0,

                                ADC_CTL_CH0 | ADC_CTL_D | ADC_CTL_IE | ADC_CTL_END);

ADC_CLOCK_RATE_FULL means sample at full rate.

    ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | ADC_CLOCK_RATE_FULL, 1);

There’s also an oversampling rate. We use the highest, which is 64.

  MAP_ADCHardwareOversampleConfigure( ADC0_BASE, 64 );

"

Please let me know if you have any recommendations to debug this issue further.

Best regards,

Jim B

  • 0
    TI__Guru*** 131470 points

    Hello Jim,

    I was doing some testing today on a EK-TM4C1294XL LaunchPad using the Differential example from TivaWare 2.2.0.295 and I am not seeing an issue with the measurements.

    To directly answer the question itself: The 0.3V drop is not reasonable to expect under typical circumstances, but I am not sure what is impacting the result.

    The full rate just means that clock is not divided, but that isn't the quickest the ADC can run at since they are running from the PIOSC and not the PLL. With very specific configuration, they could get a 32 MHz clock on the ADC which is required for the 2MSPS. Using the method they are, they would be at 16 MHz on the ADC clock and looking at 1MSPS. I am not sure how quick their signal changes, but felt that was worth bringing up.

    Given this is differential mode, I would be curious to understand the voltages actually measured at each pin, and what the ADC result is being reported as from a raw value standpoint. Also what was the previous external regulator sourcing to VREFA+?

    Did anything change with the signal chain of the inputs that could have changed the input impedance?

  • 0
    Guru 54548 points

    Hi Jim, 

    Jim Brinkhurst1 said:
    We recently switched reference voltages from an external regulator to the internal reference on the above Tiva. 

    Adding to Ralph's astute observations and testing. Perhaps customer using an external regulator versus a precision voltage reference was giving an incorrect conversion of the analog sampling. Please insure the customer was using an external but precision voltage reference and not the VDD regulator.

  • 0 in reply to Genatco
    TI__Mastermind 44440 points

    Hi Ralph

    The customer reports the applied voltage is 1.3V and the raw converted value is 0xB26.

    I'll check into the details of the external reference voltage source used earlier.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    TI__Mastermind 44440 points

    Hi Ralph

    I just received another update from the customer. They discovered a scaling error in their software that was causing the erroneous results. The issue is now closed.

    Best regards,

    Jim B