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When the DRV8350S is working with a motor, the chip will report GDUV error when the 48V power supply is turned on for about ten seconds, and the restart is useless, and the chip is damaged.
You should not be using IDRIVE source greater than 100 mA based on the rating of these MOSFETs (see this FAQ)
The VGLS capacitor is grounded to GND, not PGND. VGLS needs to be grounded to PGND since that is the same GND as VM and the MOSFETs. DRV8350 GND pin (30) should also be tied to PGND.
How are GND and PGND connected on the PCB? I recommend the connection be as close to the DRV8350 as possible.
Customer would like to know what internal principle causes the chip damage? He found that the VGLS pin state impedance of the bad veneer is abnormal. He suspects that the internal output VGLS LDO is damaged. Would you share your suggestion for this?
In the case of high gate drive current, you can overload the regulator or cause coupling back into the regulator to pump up the voltage and result in damage. The coupling path is SHx to GLx across the CGD of the external capacitor, and then through the source driver of the DRV835x into the VGLS regulator.
If the VGLS capacitor is not connected to the VGLS pin very closely, additional parasitic inductance results in the capacitance having less effective value and the ripple can cause damage to VGLS LDO.
If the VGLS capacitor GND is not tied closely to the PGND and the GND of the MOSFETs, it can result in a long trace which introduces inductance into the VGLS loop. This can cause excessive ripple when turning ON or OFF gate drivers and can cause damage.
This problem will not occur after the customer changes the 2.2ohm resistor of the gate to 75ohm. He would like to know why? Could you share your comment?
Changing from 2.2 ohms to 75 ohms reduces then gate drive current. This will relate to my first bullet point above:
In the case of high gate drive current, you can overload the regulator or cause coupling back into the regulator to pump up the voltage and result in damage. The coupling path is SHx to GLx across the CGD of the external capacitor, and then through the source driver of the DRV835x into the VGLS regulator.
The customer adjusted the size of IDRIVE on the software, from 2000ma to 100ma, the waveform has not changed during the whole process, and the situation has not improved. He had to increase the drive resistance, but this would make the dead zone very long.
Adjusting the series resistance and adjusting the IDIRVE will have the same effect. Please ensure that the customer is adjusting both the source and sink settings (there are four different registers). For example, the sink setting can be adjusted from 2000mA down to 100mA while the source setting can be adjusted from 1000mA down to 50mA.
