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DRV8308: Lock condition

Oscar Perez
Prodigy 20 points
Part Number: DRV8308

Good day,

We are developing a light vehicle using the DRV8308. it has performed well so far,except for..

The lock pin, initially I assumed it goes low when the clkin frequency matched the fgout frequency but that doesn't seem to be the case. the functional diagram in datasheet page 23 shows that lock detect doesn't take into account the clkin value at all. The diagram is not really clear, what are the conditions that will lead to the motor controller enabling sinusoidal drive and pulling the lock pin low. 

There is a frequency comparison done before the integrator but that doesn't lead to the lock signal logic. 

This is a problem for us because we have found a recurring situation where the fgout (motor RPM) is about half the frequency of clkin so the motor is spinning at about half the commanded speed but the DRV8308 has pulled the lock line low.

Our default setting values are:

REGISTER0_SYNRECT (1U)
REGISTER0_PWMF (2U)
REGISTER0_SPDMODE (0U)
REGISTER0_FGSEL (1U)
REGISTER0_BRKMOD (1U)
REGISTER0_RETRY (1U)
REGISTER1_ADVANCE (0x21)
REGISTER2_SPDREVS (100U)
REGISTER2_MINSPD (10U)
REGISTER3_BASIC (0U)
REGISTER3_SPEEDTH (5U)
REGISTER3_MOD120 (3970U)
REGISTER4_HALLRST (0U)
REGISTER4_DELAY (0U)
REGISTER4_AUTOADV (1U)
REGISTER4_AUTOGAIN (1U)
REGISTER4_ENSINE (1U)
REGISTER4_TDRIVE (1U)
REGISTER4_DTIME (5U)
REGISTER4_IDRIVE (7U)
REGISTER5_INTCLK (0U)
REGISTER5_SPDGAIN (2U)
REGISTER6_HALLPOL (0U)
REGISTER6_BYPFILT (0U)
REGISTER6_FILK1 (630U)
REGISTER7_FILK2 (1568U)
REGISTER8_BYPCOMP (1U)
REGISTER8_COMK1 (0x12C)
REGISTER9_AA_SETPT (0x08)
REGISTER9_COMK2 (0x258)
REGISTER10_OCPDEG (3U)
REGISTER10_OCPTH (3U)
REGISTER10_OVTH (1U)
REGISTER10_VREG_EN (1U)
REGISTER10_LOOPGAIN (40U)
REGISTER11_SPEED (600U)

It would be extremely helpful to hear your thoughts

Thanks

Oscar

  • 0
    TI__Mastermind 19825 points

    Hi Oscar,

    Thanks for your post! I will try to get a response to you by the end of the week.

    Regards,

    Anthony Lodi

  • 0
    TI__Mastermind 19825 points

    Hi Oscar,

    Sorry for the delay in getting a response to you, that was my fault. I will look into this more today and provide an update by the end of the day.

    Regards,

    Anthony Lodi

  • 0
    TI__Mastermind 19825 points

    Hi Oscar, 

    Oscar Perez said:
    This is a problem for us because we have found a recurring situation where the fgout (motor RPM) is about half the frequency of clkin so the motor is spinning at about half the commanded speed but the DRV8308 has pulled the lock line low.

    I find it interesting that the fgout is about half the frequency of clkin. The fact that it is half the frequency makes me think there may be a setting that causes the reference speed to be reached when clkin is half of FGOUT. Could you change FGSEL to 0 to have FGOUT trigger on every hall U change and see if that effects the FGOUT to CLKIN ratio when the driver enters LOCK mode?

    Regards,

    Anthony Lodi

  • 0 in reply to Anthony Lodi
    Prodigy 20 points

    Hi Anthony,

    Thank you for your reply and sorry for the delay.

    I took a reading of the actual RPM of the motor and it matched precisely what the the FGOUT indicated so I can trust that setting is accurate, It didn't however match the CLKIN frequency. 

    (yellow is CLKIN 50% duty cycle, pin is FGOUT) This was taken in a time where the nLOCK pin was pulled low even though the frequency isn't quite matched and the physical speed of the motor being slower than should be.

    I did end up finding that increasing the PWM frequency to 100KHz fixed the speed problem. The motor now reliably reaches the required RPM every time but that doesn't necessarily answer why the nLOCK pin would get pulled low when it is so different from the reference speed..

    I'm happy to leave it here but if you have some insight on the internal logic of the nLOCK pin it would be most helpful. 

    Thank you .

    OP 

  • 0 in reply to Oscar Perez
    TI__Mastermind 19825 points

    Hi Oscar,

    In the waveform above it looks like the FG out frequency is quite close to the frequency of clock input. You mentioned in another post that it was about half the frequency. Is there a relationship that you are seeing between the frequency of the clock input and the frequency of FGOUT at which the driver pulls nLOCK low? Does the FGOUT frequency becomes more out of sync with the clock frequency for higher clock frequencies? 

    Regards,

    Anthony Lodi