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DRV8323: Motor Rattling Noise

Simone Palombi
Prodigy 10 points
Part Number: DRV8323
Other Parts Discussed in Thread: DRV832X

Hello team,

I am using the DRV8323HRTAR (no SPI) to drive a BLDC motor.

While the motor spins, it makes a strange rattling noise and I am trying to solve this issue.

I have implemented a trapezoidal upper modulation control with speed retroaction.

Analyzing some data (2-ch scope and CAN at 1ms cycle time) I am noticing that:

- Bridge A is behaving differently than B and C

- Every time I turn off a low side mosfet, there is a voltage spike on the high side voltage gate

- While the high side mosfet is on, also the low side is on

CAN Data:

SOx = current measured via the shunt resistor by the DRV

Scope Data:

- All the waveforms are the gate voltage measured with reference to ground

The DRV is configured as follow:

- GAIN = 20V/V

- MODE = 6x PWM

- IDRIVE = 120/240mA

- VDS = 0.6V

- Shunt = 2mohm

- No fault triggered by the NFAULT pin

Please let me know if you need any additional information.

Thank you

Simone Palombi

  • 0
    TI__Mastermind 26046 points

    Hi Simone,

    Simone Palombi said:
    I have implemented a trapezoidal upper modulation control with speed retroaction.

    What is speed retroaction?

    Simone Palombi said:
    Every time I turn off a low side mosfet, there is a voltage spike on the high side voltage gate

    This is indicative of coupling into the high side gate voltage, perhaps when the HS FET turns on that there is coupling into VGSH (high-side gate voltage)

    Simone Palombi said:
    While the high side mosfet is on, also the low side is on

    This is also indicative of coupling into the low-side gate voltage (VGSL) when the high side turns on... this is caused by parasitics in the motor current path, too fast of a VDS slew rate when the FET is turned on (too high of IDRIVE current), or not enough sink current to hold the low-side FET to VGSL = 0V when the high-side FET is switching. 

    Can you confirm if your IDRIVE setting is appropriate based on the FETs used in your application? e2e.ti.com/.../faq-selecting-the-best-idrive-setting-and-why-this-is-essential

    Please review this document to help debug higher power designs if high motor current is used with the DRV832x: www.ti.com/.../slvaf66

    How is your trapezoidal commutation working, do you use Hall sensors or a sensorless algorithm? 

    Thanks,
    Aaron

  • 0 in reply to Aaron Barrera
    Prodigy 10 points

    Hello Aaron,

    Speed retroaction: I am controlling the speed rather than torque through a PID which is well calibrated since I am capable to reach and maintain the speed fairly well.

    I use HALL sensors within my algorithm through which I compute both the switching pattern and the motor speed. You can see the hall sensor in the previously attached image named PhaseA_sts, PhaseB_sts and PhaseC_sts. The motor rotates counterclockwise.

    Given Qgd of the mosfet 11nC (typical) or 16nC (maximum), and given a switching frequency of 24kHz, from the given formula 120/240mA looks like a reasonable value. Do you confirm that leaving the IDRIVE pin disconnect determines this setting?

    Further info: the system power supply is 40V, maximum current 10A continous, 20A 30s, 30A 10s.

    I am running this test targeting 200rpm, the motor consumes around 0.5A to rotate at this speed. I have tested the motor up to 700rpm, when the rattling noise seems to reduce. Maximum speed is 2000rpm.

    The main difference wrt guidelines in my design I found so fare is the trace of the gate wire, mine is 0.3mm and suggested is 0.5mm (minimum 0.38mm).
    I don't have gate resistors, nor mosfet in parallel.

  • 0 in reply to Simone Palombi
    TI__Mastermind 26046 points

    Hi Simone,

    Thanks for your feedback. 

    Simone Palombi said:
    Given Qgd of the mosfet 11nC (typical) or 16nC (maximum), and given a switching frequency of 24kHz, from the given formula 120/240mA looks like a reasonable value. Do you confirm that leaving the IDRIVE pin disconnect determines this setting?

    Yes this is correct. 

    Can you share your schematic to review?

    Thanks,
    Aaron

  • 0 in reply to Aaron Barrera
    Prodigy 10 points

    Please find it attached

  • 0 in reply to Simone Palombi
    TI__Mastermind 26046 points

    Hi Simone, 

    I couldn't find a reliable datasheet of the FETs you are using, but I think it may have one of these packages, can you confirm? 

    If so, these leaded FET packages have a lot of gate inductance and require much smaller IDRIVE current. Qgd for the datasheet I found is around 6nC (https://www.digikey.com/en/htmldatasheets/production/579889/0/0/1/ipx054-57n06n3-g.html?site=US&lang=en&cur=USD), which means gate current should be around 6nC/200nS = 30mA. I would see if you can find a way to connect the IDRIVE pin to a lower gate current setting, such as tie to GND. 

    It looks like from your first waveform, your low side bridge A is turning on when you turn on your high-side bridge A. This look to be dV/dt coupling into the low-side gate if you are turning on the FETs too fast or slewing too much motor current quickly. Having a slower turn on time (lower IDRIVE) can help or reducing parasitics in the gate drive outputs and motor phase currents. 

    Would you mind sharing PCB layout over the thread or you can send it to me privately through personal message? If thin & long gate drive current traces are used, then this can also add inductance to the gate drive path and make gate drive turn on/turn off more noisy. 

    Thanks,
    Aaron

  • 0
    Prodigy 10 points

    Hi Aaron,

    please find the datasheet of the mosfet attached.

    Infineon-IPP057N08N3-DS-v01_02-en-1227177.pdf

    About the PCB, it is a 4 layer, ground panes in all layers. I can share parts of it, the one related to the gate traces.

    All gate traces are 0.3mm width

    Low Side Bridge A is 30.7mm long

    High Side Bridge A is 46.6mm long

    Low Side Bridge B is 40.7mm and High Side bridge B is 47.8mm

    Low Side Bridge C is 54mm and High Side bridge C is 69.2mm

  • 0 in reply to Simone Palombi
    TI__Mastermind 26046 points

    Hi Simone,

    You will have some gate drive issues using the TO220/TO262 package FETs. These introduce significant inductance into the leads of the package and severely limit the gate drive capability provided. Additionally, using thin gate drive traces also limits the source/sink gate drive current from the DRV832x. I would start at the lowest IDRIVE setting by tying the IDRIVE pin to ground and monitoring your gate waveforms on each half bridge to determine if the gates are turning on/off correctly. 

    For instance, monitor on an oscilloscope (if you have 2 probes)...

    GHA & GLA with respect to GND

    GHB & GLB with respect to GND

    GHC & GLC with respect to GND

    ...and ensure there are no "shoot through" events when the FETs turn off. You'll want there to be enough dead time between the high-side FET turning off and the low-side FET turning on. You'll need to zoom in pretty close (100ns/div) to see this behavior. 

    One thing to try as well is adding dead time to the MCU inputs. The dead time in the H/W device defaults to 100ns which may not be enough. Could you increase this to a higher value, like 500ns, to see if the rattling goes away?

    Thanks,
    Aaron

  • 0 in reply to Aaron Barrera
    Prodigy 10 points

    Hello AAron,
    A lower IDRIVE did his job, I don't see the spikes on the low side gate anymore.
    Though the rattling noise is still there.

    Bridge A (blue low side, orange high side)

    Bridge B

    Bridge C

    I am also still wondering why the high side gate has a spike to 40V every time the low side is turned off.

    I also tried to increase the dead time, without noticing any positive effect.

    Thank you

    Simone

  • 0 in reply to Simone Palombi
    TI__Mastermind 26046 points

    Hi Simone, 

    Just a reminder that since you are using VM=40V and supplying up to 30A continuous current for 10 seconds, the layout and system should be well designed to ensure that any transients that appear do not exceed the VM or SHx abs max rating of 65V.

    Since the high side gate spikes to 40V, it is likely that SHx is 40V momentarily to keep the high side VGS voltage = 0V, so GHx also spikes to 40V momentarily. There may be too much dead time now, because during dead time both FETs are Hi-Z and there is weak gate holding currents. SHx is likely staying high at 40V for a little too long because current cannot flow through the LS FET and may flow the supply through the HS body diode as shown in blue. 

    Since the dead time cannot be reduced, could you try further reducing the IDRIVE current setting, add a small series resistor (1's of ohms) in the high side gate drive paths, or add a small amount of gate-to-source capacitance (Cgs) at the high-side FET in order to increase the gate rise/fall time? I want to effectively reduce the dead time as much as possible. 

    Thanks,
    Aaron

  • +1 in reply to Aaron Barrera
    TI__Mastermind 26046 points

    Actually Simone, the source of your rattling appears to be from uneven Hall sensor commutation states.

    Please check your Hall sensor waveforms. I used the same arrow length to compare the electrical period of each state. They are uneven. This means:

    - Your Hall sensors are misaligned
    - The inductance of your motor is introducing a lag phase angle

    Please ensure that the Hall signals are equal in electrical period and physically placed evenly between the motor phases. Any misalignment in Hall sensors introduces rattling. You may have to implement a lead angle delay in software to correct inductive lag if the motor phase current does not align with the motor phase voltage: https://www.ti.com/lit/pdf/slaa561

    Thanks,
    Aaron

  • 0 in reply to Aaron Barrera
    Prodigy 10 points

    Hello Aaron,

    thank you for your support, that solved my issue, it was not necessary to further increase the gate rise/fall time.

    Thank you

    Simone

  • 0 in reply to Simone Palombi
    TI__Mastermind 20125 points

    Hi Simone,

    Glad to hear that Aaron was able to help resolve your issue!

    Regards,

    Anthony Lodi