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DRV8308: Relationship between SPI and ENABLE signals

tatsuro tokugawa
Prodigy 100 points
Part Number: DRV8308

Hi,

I'm evaluating "DRV8308" now.

In the attached figure, "tAWAKE" is specified as 1ms (max) as the one of timing requiremet of SPI.
Does this mean that the ENABLE signal must be set to "H"(ENPOL=0) 1ms before the SPI read and write?

Best regards.

  • 0
    TI__Mastermind 18916 points

    Hi Tokugawa-san, 

    I believe your interpretation of the datasheet spec should be correct. 

    Generally speaking, many of our DRV devices have integrated regulators, such as charge-pumps and other LDO regulators. 

    • These are used for various purposes such as digital-logic power, gate-drive overvoltage supply, etc... 
    • When the device is powered off or placed into sleep mode, these regulators may be unpowered. 
    • Therefore, waking up the device (e.g. EN=H) may initiate the process of waking up the device (and these regulators) and it takes time to charge up the regulators. 
    • Once they are fully charged up, the device is ready to use & operate the motor. 

    The reason for that T_AWAKE spec is likely to give the device sufficient time to power up the charge pump, such that the user gives the system adequate time to prepare gate overdrive voltage (VCP) before they start expecting commutation commands to toggle the DRV outputs.

    Please let us know if this resolves your question. Thanks! 

    Best Regards, 
    Andrew 

  • 0 in reply to Andrew Liu
    Prodigy 100 points

    Andrew-san

    Thank you for your reply.

    I still have some questions as follows.

    1. In case that I activate the Enable and write some register via the SPI, then I inactivate the Enable, does the register value still be retained?
    2. When controlling with "Clock Frequency Mode", do I need to activate the ENABLE 1ms before the CLKIN transmission?
    3. When I send a reset by the RESET signal, do I need to activate the Enable 1ms before?
    4. "tSPI" is defined in the SPI timing requirements.
    It says "Delay from power-up", and I think that the power is naturally turned on at the timing of activating the ENABLE, but I do not know why it is smaller than 10us and 1ms.

    Best regards,

    Tatsuro

  • 0 in reply to tatsuro tokugawa
    TI__Mastermind 18916 points

    Hi Tokugawa-san, 

    Some more answers below: 

    1. For the datasheet definition, these three things are what can cause the internal logic (including register values) to reset:
      1.  I think ENABLE pin alone won't cause the registers to reset, but datasheet will give you the most accurate answer 
    2. CLKIN 
      1. I would suggest waiting 1ms first before doing anything that would involve motor output switching. 
      2. I believe the CLKIN pin is the main PWM command that will cause the gate-driver to operate, 
        1. so if you send a CLKIN command before 1ms, and the regulators are not fully powered up, may cause some type of fault
    3. Datasheet screenshot above will explain the RESET signal operation. Might not need 1ms since RESET pin doesn't involve gate-driver operation. 
    4. t_SPI timing definition
      1. SPI requires digital logic availability to function, and may not depend on ENABLE 
      2. if the device power pin (VM) is OFF, the digital logic is not powered on
        1. therefore it takes some time after VM power-up for digital logic & SPI to be ready
      3. if the device RESET=H, then the device digital logic is being reset
        1. it takes some time after RESET=L to 'stop resetting' and power up the digital logic again, so that SPI can be ready for use
      4. digital logic takes much less time to power-up than regulators like charge-pump
        1. that's why SPI (digital) may only need to wait 10uSec to be ready, but gate-drive behavior (analog) needs 1ms to be ready 

    Best Regards, 
    Andrew 

  • 0 in reply to Andrew Liu
    Prodigy 100 points

    Andrew-san

    Thank you for your reply.
    I have one more question to ask.

    > 3. Datasheet screenshot above will explain the RESET signal operation. Might not need 1ms since RESET pin doesn't involve gate-driver operation.

    The logic reset is described in the attached diagram as follows:
    "3. When the RESET pin is high while ENABLE is active."

    Should ENABLE pin be "H(active)" while RESET pin is set to "H"?
    Is more than 20us pulse length okay for the RESET and the ENABLE?

    Best Regards,

    Tatsuro.

  • 0 in reply to tatsuro tokugawa
    TI__Mastermind 18916 points

    Hi Tokugawa-san, 

    In order for a commanded device-RESET to occur, 

    1. ENABLE=H first
    2. then either immediately afterwards, or after some delay, can toggle RESET=H 
    3. Deglitch definition
      1. the RESET pin must remain HIGH after rising edge (assertion) in order for the reset sequence to proceed
      2. the RESET pin must remain LOW after falling edge (de-assertion) in order for reset sequence to end 

    Best Regards, 
    Andrew 

  • 0 in reply to Andrew Liu
    Prodigy 100 points

    Andrew-san

    Thank you for your reply.

    >3. Deglitch definition
    > the RESET pin must remain HIGH after rising edge (assertion) in order for the reset sequence to proceed
    > the RESET pin must remain LOW after falling edge (de-assertion) in order for reset sequence to end

    That mean more than "10us" pulse length is okay for the RESET?

    Best Regards,

    Tatsuro.

  • +1 in reply to tatsuro tokugawa
    TI__Mastermind 18916 points

    Hi Tokugawa-san, 

    That explanation looks correct, and your diagram explains it well. 

    Yes, more than 10us of pulse length is actually required* in order for the RESET to process, and this is called 'deglitch' time. 

    The purpose of deglitch in this case is to ensure that brief noisy transients on RESET pin (<10us) don't cause the device to RESET accidentally 

    Best Regards, 
    Andrew