DRV8303: how to modify the current amplification default scale

Hey Cherry,

Thank you for posting your question to the E2E.

I will discuss with the team and aim to provide feedback by next week Wednesday.

Best Regards,

Akshay

Hey Cherry,

Thank you for your patience.

• To change the gain setting you would need to send instructions through SPI. In address 0x03.

Please refer to the Table 11 of the following datasheet.

https://www.ti.com/lit/ds/symlink/drv8303.pdf

• The current amplification is set on register 3 not register 2, could you clarify which register you are referring to? The GVDD undervoltage feature only triggers if the voltage is below 7.5V. So, it is likely that the SPI registers aren’t resetting due to GVDD undervoltage. It is possible that there is a DVDD undervoltage which resets status registers. Another instance when SPI registers are reset is when EN_GATE goes high or if there is a PVDD undervoltage.

• When driving the MOS tube, the GVDD might be dropping because the IDRIVE is set on the highest level (default condition). Please check if that is the case and consider lowering the IDRIVE. It might also help to add a substantial bulk capacitor to prevent large GVDD dips.

Please check if any faults are being triggered on SPI registers.

Hope this offers some clarification.

Best Regards,

Akshay

Hello Akshay,

Thanks for your support!

Akshay Rajeev Menon said:

• To change the gain setting you would need to send instructions through SPI. In address 0x03.

Please refer to the Table 11 of the following datasheet.

The SPI instruction does modify the gain, but after some fault or power up/down, the current gain is restored to the default of 10 V/V, so the gain factor appears to be written into ram. While in real applications, the customer needs to have a final current gain of 80 V/V, except for power up/down.

Akshay Rajeev Menon said:

The current amplification is set on register 3 not register 2, could you clarify which register you are referring to? The GVDD undervoltage feature only triggers if the voltage is below 7.5V. So, it is likely that the SPI registers aren’t resetting due to GVDD undervoltage. It is possible that there is a DVDD undervoltage which resets status registers. Another instance when SPI registers are reset is when EN_GATE goes high or if there is a PVDD undervoltage.

In register 2 and address is 0X03.

When the three-phase inverting MOS tube is actually driven, a pass-through of the upper and lower MOS tube in phase B occurred, causing the nFAULT pin to be pulled low by 800 us and then back to high again (because the device controls all MOS off after phase B MOS pass-through).
The current gain factor is restored to 10 V/V (at power up, the gain factor of 80 V/V has been written by the SPI communication and the SPI reply data is correct).

It is dangerous to change the current gain factor suddenly, so customers would like to know what conditions cause the current gain factor to change and how to modify and write the default gain factor?

Akshay Rajeev Menon said:

When driving the MOS tube, the GVDD might be dropping because the IDRIVE is set on the highest level (default condition). Please check if that is the case and consider lowering the IDRIVE. It might also help to add a substantial bulk capacitor to prevent large GVDD dips.

Understood.

Thanks and regards,

Cherry

Hi Cherry,

Do you need assistance on this thread? If not, please mark as "Resolved". 

Thanks,
Aaron