• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 29 subscribers
  • Views 256 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8308: LOCKn assert condition

Hirotaka Matsumoto
Guru 27545 points
Part Number: DRV8308
Other Parts Discussed in Thread: DRV8307

Hi all 

Would you mind if we ask DRV8308?

Could you let us know the LOCKn assert condition(LOCKn=Low)?

The datasheet shows "After a constant speed is reached, the LOCKn pin is pulled low and only one Hall sensor becomes used; " only.

As the background of this question, at the our customer site, there are following situations;
-CLKIN=300Hz, FGOUT=300Hz ->  LOCKn assert
-CLKIN=300Hz, FGOUT=70Hz  -> (after a certain time) -> LOCKn assert

So, it seems that LOCKn assert is not relation between CLKIN and FGOUT.
After FGOUT value becomes constant, LOCKn asserts.


Kind regards,

Hirotaka Matsumoto

  • +1
    TI__Mastermind 24405 points

    Hi Hirotaka-san,

    This is a pretty old device and the support is limited. Looking at the datasheet, my understanding is that the LOCKn is driven low when a spinning motor reaches a consistent speed based on the period of Hall U. I don't think there is a specific speed threshold number defined for this device. DRV8307 effectively has a 12.5% speed threshold (SPEEDTH) and requires 4 Hall_U periods to lock. The HALL_U frequency must be faster than 2Hz for lock to occur.

    Regards,

    Vishnu

  • 0 in reply to Vishnu Balaraj
    Guru 27545 points

    Vishnu san

    Thank you for your reply.

    This is a pretty old device and the support is limited.
    I don't think there is a specific speed threshold number defined for this device.
    ->Ok, we got your circumstance. However, we want definite answer. 
       Is DRV8308's LOCKn assert condition following?

    <DRV8308's LOCKn assert condition>
    -Threshold(*1) : Within speed threshold (SPEEDTH) 
    -Period(term) : 4 Hall_U periods(2.56ms‐652.8ms×4 ? )
    -HALL_U frequency : Faster than 2Hz

    And then, we would like to confirm about speed threshold(SPEEDTH).
    This threshold indicates "HALL_U frequency".
    So, there is no relation to FGOUT or CLKIN.
    Is our recognition correct?

    Kind regards,

    Hirotaka Matsumoto

  • +1 in reply to Hirotaka Matsumoto
    TI__Mastermind 24405 points

    Hirotaka-san,

    I believe your understanding is correct but would highly encourage to test this on bench for the confirmation?

    Regards,

    VIshnu

  • 0 in reply to Vishnu Balaraj
    Guru 27545 points

    Vishnu san

    Thank you for your reply.
    OK, we will encourage the customer to test it.

    Kind regards,

    Hirotaka Matsumoto