Hi
My customer have some questions regarding Leakage current from control pin to VM at VM=0V.
I found the following E2E session.
I have additional questions.
1. At VM=0V and control pins (nSLEEP, Enable, STEP, DIR ) = 3.3V, Does the device have any issue or concern?
2. At the above conditions, Is there any leakage current to VM pin(VM=0V)?
Logic inputs have only low side diode and Pulldown resister(100k) in the datasheet, I think, no leakage current to VM. Is it correct?
3. Normal case, for example at VM=24V, is there any internal path from VM to control pin?
4. Do other pins(RREF etc) have any leakage current to VM pin or other pins(other than GND)?
5. Do you have any concern for the the control & power up sequence? Is this device the sequence free?
Thanks
Muk