TPS40077: Schematic review

Denny Huang 

To review the compensation, please use the compensation design tool - https://www.ti.com/product/TPS40077#design-development 

Looking over the rest of the schematic:

1) You have included series resistors on LDRV, HDRV and SW, but not one on BOOT.  If you believe you will need to be able to control the rise and fall timing of the switching node, you should include a resistor in series with the BOOT pin.  Place this between the IC pin and the D1 connection so that the recharge current from Driver Bypass (DBP) to the boot-strap capacitor (C1198) does not have to pass through the current limiting resistor.

2) The UVLO level set by the KFF resistor (R996) is low for a 12V output.  WIth RT = 165k (300kHz) and RKFF = 165kHz, the UVLO level is 7.3V.  It is generally advisable to have the UVLO voltage set higher than the intended VOUT value.

3) You asked about a recommendation for Q10 and Q11, but there are MOSFET part numbers listed.

Hi John

I appreciated your great support.

Many thanks

Hi peter

The customer would like to confirm the parameter of excel file correspond to user's guide.

The type III compensator refer from compensation design tool - https://www.ti.com/product/TPS40077#design-development 

Type-III Compensation With the TPS40077 refer from datasheet page.29.

1. Could you help to check the signal(Vo,FB and COMP) are right? 

Many thanks

Denny

Denny Huang 

Yes, those are the correct connections.

R1 in parallel with C1 + R2 are from Vout to FB

Rbias is from FB to SGND

C3 in parallel with R3 + C2 are from FB to COMP

From the original schematic, as best I can read it.

R1 is R1002 = 162k

R2 is R1005 953

R3 is R1001 3.48k

Rbias is R1004 10k

C1 is C1195 2200pF

C2 is C1194 3900pF

C3 is C1193 680pF

Denny Huang 

The schematic looks better now.

Looking at the compensation spreadsheet, I had to change the part number to TPS40077, and after doing do, I noticed that the phase margin at the L-C resonance is very low.  Looking into why, I can see a couple of issues:

The ESR value for the 22uF ceramic capacitors is entered as 30mΩ, which is really high for ceramic capacitors, so I tried adjusting this to 3mΩ for a more realistic value.  Also, the L-C double pole is at about 3kHz and the loop's compensation zeros are set at 24kHz, so there is no phase boost at the L-C resonance.

Using the manually enter Poles and Zeros feature, I set the poles down at the 3kHz L-C resonance to give phase boost at the L-C resonance, and I get a much better looking loop.  It also has higher bandwidth.

TPS40KType III Loop Stability kVenable_sluc263c-071312_ARC_0706_PJM.xls