TPS3431-Q1: Can we keep EN pin floating to get logic low?

Jay Sun

Part Number: TPS3431-Q1

Hi,

There are some cases in my application that the driving circuit for EN pin will become floating when I expect the EN should be logic low.

From the datasheet, EN pin is internally pulled up to VDD. Besides, I have to minimum the driving current of EN pin.

Therefore, I am not sure if it is required to externally pulI down EN pin for stable logic low when external driving is floating.

If an external pull down is required, please let me know the maximum allowed resistance to minimize current consumption.

Thanks.

over 3 years ago

0 Ben C over 3 years ago

TI__Mastermind 35955 points

Hi Jay,

Is it possible to use a pull-down NMOS FET in your application?

Ben

0 Jay Sun over 3 years ago in reply to Ben C

Prodigy 60 points

Hi Ben,

Sorry, using a pull-down NMOS is not a option for my case. Could you suggest me the appropriate resistance for pull down?

0 Ben C over 3 years ago in reply to Jay Sun

TI__Mastermind 35955 points

Hi Jay,

I dont think it is feasible to add a pull down resistor on the EN pin. The current that comes out of the EN pin when grounded is 620nA. To consider a VIH for the EN pin is 0.8V. If we do some simple math, the resistance to meet the VIH spec is 0.8V/620nA = 1.29Mohms. Also, 1.29Mohms value would not be a good pulldown resistor.