TPS68470: power-up timing sequence

Hi Henry, the team is looking into this request and should be able to provide feedback by tomorrow.

Hi Henry,

To follow up on Brandon's comment, I'm in the process of confirming whether this sequence is acceptable:

Henry Wang3 said:

SDA/SCL => RESET_IN => 3V3_SUS/3V3_VDD

By "MCLK" I assume you are referring to the PMIC HCLK_A and HCLK_B outputs - please correct me if I'm wrong. 

1. Is the customer following the steps in section 3.5.2 of the EVM User's Guide to enable the HCLK outputs at 40 MHz? If not, could you please share what procedure the customer is using?

Link to the EVM User's Guide: https://www.ti.com/lit/ug/slvuaa8/slvuaa8.pdf

Thanks,

Gerard

Hi Sir,

The customer replied to your questions as below.

1. Is the customer following the steps in section 3.5.2 of the EVM User's Guide to enable the HCLK outputs at 40 MHz? If not, could you please share what procedure the customer is using?

-> We have set it to 19.2MHz, not 40MHz.
However, the NG PMIC outputs 40MHz.
Or NG PMIC not outputs HCLK.
Please refer to topic "TPS68470: PMIC is malfunctioning" for procedure.

When we changed the settings from "PLL Multiplier" to "Internal Oscillator", the NG module could be work normally, why?

Hi,

This points to an issue with the procedure or the external oscillator. I don't see any issues with the POSTDIV, XTALDIV, and PLLDIV values you are using. However, the sequence of commands does not match the procedure in the EVM User's Guide (see steps 1-10 in section 3.5.2).

1. First, please re-organize the I2C sequence to match the procedure in steps 1-10 of section 3.5.2.

If the behavior still occurs:

1. Can you please share the oscillator part number? 
2. Have you verified the 20 MHz oscillator output at the OSC_IN and OSC_OUT pins?

Thanks,

Gerard

Hi Sir,

Another question about the I2C pull-up.

At the power-up sequence, could we use a separate pull-up supply of 3.3V on SDA(F5) and SCL(G5)?

It's mean the power-up sequence as below.

3V3_SUS, 3V3_VDD and a separate 3.3V => IO_OUT powers up => configure GPIOs

Hi Henry,

Please expect a response by EOD tomorrow.

Thanks,

Daniel W

Hi,

Typically the LDO_IO output is used as the I2C pull-up voltage for SDA (F5) and SCL (G5). Out of curiosity, is there a reason this application has an external 3.3 V pull-up voltage?

I will check if there are any concerns with using an external 3.3 V supply in the power up sequence you are describing, and provide an update tomorrow. 

Thanks,

Gerard

Hi Sir,

The customer replied to your questions as below.

This points to an issue with the procedure or the external oscillator. I don't see any issues with the POSTDIV, XTALDIV, and PLLDIV values you are using. However, the sequence of commands does not match the procedure in the EVM User's Guide (see steps 1-10 in section 3.5.2).

1. First, please re-organize the I2C sequence to match the procedure in steps 1-10 of section 3.5.2.=> Could I know there have any side effect? if we have some sequence of commands does not match the procedure.     

If the behavior still occurs:

1. Can you please share the oscillator part number?  =>  20MHz.4P.12pf/30ppm.FujiCom.FSX3M 20.000000M12FAQ
2. Have you verified the 20 MHz oscillator output at the OSC_IN and OSC_OUT pins?

Hi Sir,

Any update for below questions?

1. Only 3V3_SUS and 3V3_VDD are specified in the datasheet 8.3.1 ) of TPS68470, could you tell us the detailed power sequence requirements? need the timing sequence between the I2C pull-up and the Reset pin?

2. When the I/O power is done before the 3V3_SUS and 3V3_VDD, what kind of malfunction can occur with the power sequence on the below?  (SDA/SCL => RESET_IN => 3V3_SUS/3V3_VDD)

Hi Sir,

From No. 18, CON_XTAL_C[2:0] = 101 = 10 pF. As such, the total load capacitance seen by the oscillator outputs is 12 pF + 7 pF + 10 pF = 29 pF. The extra capacitance could be causing issues in certain cases. Is it possible to reduce the load capacitance on the NG board to see if the issue is still present?

=> Yes, it is still present. We thought this issue follows the NG module, right?

Hi,

Yes this was my initial thought based on your table. Have you tried swapping the PMIC and/or oscillator from the OK module to the NG module to see if the issue is resolved (in other words, the A-B-A swap)?

Thanks,

Gerard

Hi Sir,

Yes this was my initial thought based on your table. Have you tried swapping the PMIC and/or oscillator from the OK module to the NG module to see if the issue is resolved (in other words, the A-B-A swap)?

=> Yes, we have swapped the PMIC on NG and OK modules had seen the issue is resolved.

Hi,

Was there any difference when swapping the oscillator from the OK module to the NG module?

Going forward please note the recommendation not to assert RESET_IN until 3V3_SUS/3V3_VDD are applied. 

Thanks,

Gerard