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UCC28220: UCC28220 Simulation problem

You Jim
Prodigy 80 points
Part Number: UCC28220

We have some problems to clarify about IC ucc28220.

 We use simplis to build ucc28220 model to simulate Interleaved boost converter. After the parameter adjustment for compensation, the Bandwidth simulation result can only be up to around 1khz with enough phase and gain margin.

1. No matter how we adjust the parameters, Bandwidth cannot be above 1khz, Is this Bandwidth limited by the controller IC?

 According to the datasheet of ucc28220.

2. What is the detailed operation principle here?

3. Are there simulation examples for simplis to build? Or is there a practical circuit application that duty cycle can reach 90%?

SPEC
Input voltage: 13.98 V
Output voltage: 48 V
Output current: 20.3 A
Frequency: 200k Hz

  • 0
    TI__Expert 3160 points

    Hi Jim

    The ucc28220 model is from TI or you set up this model on your own?

  • 0 in reply to Jerry Xu
    Prodigy 80 points

    The model is set by myself, according to the block diagram in ucc28220.

  • 0 in reply to You Jim
    TI__Expert 3160 points

    We doesn't have simplis model yet. Rchar and Rdischar are used to set the maximum value of duty cycle that the IC can reach. For your spec, the duty cycle is equal to 0.71. So what's the maximum value of duty cycle in your simulation model? In my opinion, the bandwidth can't be affected by duty cycle if the output voltage can keep stable. Besides, UCC28220 use current mode control. So the bandwidth will be easy to promote compared to voltage mode control. Because the power stage model is a first-order system. Therefore, maybe the IC mode you set up has some issue.

  • 0 in reply to Jerry Xu
    Prodigy 80 points

    My simulation result has a duty cycle of 0.73, which is a reasonable duty. What is the maximum programmable duty cycle of this IC?

    Need more duty when the circuit is operating dynamic.

  • 0 in reply to You Jim
    TI__Expert 3160 points

    20% oscillator duty cycle corresponds to a 60% maximum duty cycle at each output, where an 80% oscillator duty cycle yields a 90% duty cycle clamp at each output. I think 90% duty cycle can meet your requirement. If you still think the duty cycle lower the bandwidth, you can adjust the output voltage such as 20V to verify your suspect, then the duty cycle will not be a constraint.